5 DC-DC PCB layout suggestions
In the application design of DC-DC chips, whether the PCB layout is reasonable or not has a crucial impact on whether the chip can show its performance. Unreasonable PCB layout will cause chip performance to deteriorate, such as decreased linearity (including input linearity and output linearity), decreased load capacity, unstable operation, increased EMI radiation, increased output noise, etc. More serious problems may occur. Directly causing damage to the chip.
Generally, the user manual of DC-DC chips will have corresponding PCB layout design requirements and layout schematics. This time we will take the synchronous BUCK chip as an example to briefly talk about PCB Layout design in DC-DC chip application design. Points.
1. Pay attention to the high current path of the chip operation
DC-DC chip layout needs to follow a very important principle, that is, the area of the high-current loop of the switch should be as small as possible. In the BUCK topology shown in the figure below, we can see that there are two large current loops during the chip switching process. Red is the input loop and green is the output loop. Each current loop can be regarded as a loop antenna, which radiates energy externally and causes EMI problems. The size of the radiation is proportional to the loop area.
(Note: When the chip pin setting is not enough to allow us to take into account both the input loop and the output loop, for BUCK, priority should be given to wiring the input part of the loop. Because the current in the output loop is continuous, and in the input loop The current jumps, which will produce a large di/dt and cause a higher possibility of EMI problems. If it is a BOOST chip, the output loop wiring should be given priority.)
2. Configuration of input capacitor
① For the BUCK chip, in order to make the input loop as small as possible, the input capacitor should be placed as close to the chip pin as possible;
② In order to make the capacitor filtering effect better, let the power pass through the input capacitor first and then enter the chip;
③ The large-capacity capacitor used in CIN generally has poor frequency characteristics, so a high-frequency decoupling capacitor CBYPASS with good frequency characteristics should be connected in parallel with CIN;
④ In the case of a power supply with a small current capacity (IO ≤ 1A), the capacity value also becomes smaller, so sometimes a ceramic capacitor can be used to have both CIN and CBYPASS functions;
3. Inductor configuration
① For the BUCK chip, in order to make the input loop as small as possible, the inductor should be placed close to the SW pin of the chip;
② Use copper-clad wiring to reduce parasitic inductance and resistance;
③ The SW node must handle large currents based on its area to prevent the copper foil area from acting as an antenna and increasing EMI;
④ Do not run sensitive signal lines near the inductor;
⑤ As for the bootstrap circuit, the bootstrap circuit should be as close to the SW pin as possible to shorten the entire high-frequency circulation path;
Attached is the corresponding relationship between the line width, copper thickness and passing current of the PCB board when the temperature rises by 10°C for reference.
4. Configuration of output capacitor
In a buck converter, since an inductor is connected in series to the output, the output current is smooth;
The output capacitor is placed close to the inductor;
5. Feedback path wiring
① Usually the voltage dividing resistors at the FB feedback network use K-level, 10K-level or hundreds of K resistance values. The larger the resistance value, the more susceptible to interference. It should be kept away from various noise sources such as inductors, SW, freewheeling diodes, etc. ;
② The signal ground of the FB and COMP pins should be isolated as much as possible from the power ground carrying large current, and then connected at a single point. Try not to let the ground of the large current signal interfere with the ground of the small signal current;
③ The voltage dividing resistor of FB must be sampled from VOUT, and the sampling point must be close to the output capacitor to obtain a more accurate actual output voltage value;
#DCDC #PCB #layout #suggestions
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