A deep dive into the latest in DDR5 test technology
Author: Shen Chen
DDR SDRAM is a double data rate (DDR) synchronous dynamic random access memory (SDRAM). As one of the most important core components in modern digital systems, it is widely used. From consumer electronics to commercial and industrial equipment, from terminal products to data centers, it is used as a cache for CPU data processing operations. In the past 20 years, it has developed from SDRAM to DDR RAM, and from DDR to the current DDR5. Each generation of DDR technology has achieved significant progress in various aspects such as bandwidth, performance and power consumption, greatly promoting computing performance. improvement.
2. DDR standard development and introduction to DDR5
Figure 1 shows the development history and signal characteristics of RAM (Random Access Memory) over the past 20 years. In the SRAM era, due to the lower signal rate, we were more concerned about the fan-out of the signal and the capacitive load caused by the wiring. In the DDR1/2/3 era, with the continuous improvement of signal rates, the traditional method of circuit analysis using lumped parameters has become increasingly insufficient. We are more concerned about the establishment and hold time of the signal and the delay skew between signal lines. In the DDR4 era, transmission channels such as PCBs and connectors with limited bandwidth weaken or completely remove the high-frequency components in the original signal, causing the signal to appear on the time domain waveform as edge slowdown, ringing, or overshoot. We need to pay more attention to the eye diagram of the data, the receiving end template and the bit error rate as we do when analyzing traditional serial data. With the development of AI, machine learning and 5G, previous DDR4 technology has begun to seem inadequate. Nowadays, the fifth generation of DDR5 high-speed I/O data transmission is beginning to be marketed on a large scale.
Figure 1 DDR standard development and signal characteristics evolution
2.1 New features of DDR5
As shown in the table below, DDR5 brings a series of key performance improvements compared to DDR4, and also brings new design challenges.
Table 1 DDR4 and DDR5 comparison (from Rambus)
2.1.1 Speed improvement
In recent years, the scissor gap between the development of memory and CPU performance has become larger and larger, and the demand for memory bandwidth has become increasingly urgent. DDR4 can reach a transfer rate of up to 3.2 GT/s at a clock frequency of 1.6GHz, and the original DDR5 increased the bandwidth by 50% to a transfer rate of 4.8 GT/s. The data transfer rate of DDR5 memory will eventually reach 8.4 GT/s.
2.1.2 Voltage reduction
Lowering the operating voltage (VDD) helps offset the increase in power consumption caused by high-speed operation. In DDR5 DRAM, the registered clock driver (RCD) voltage is reduced from 1.2 V to 1.1 V. The command/address (CA) signal changes from SSTL to PODL, which has the advantage that no static power is consumed when the pin is in the high state.
2.1.3 DIMM new power architecture
When using DDR5 DIMMs, power management is moved from the motherboard to the DIMM itself. DDR5 DIMM will install a 12 V power management integrated circuit (PMIC) on the DIMM, making the system power load more granular. The PMIC distributes the 1.1 V VDD supply, which helps improve signal integrity and noise by providing better power control on the DIMM.
2.1.4 DIMM channel architecture
DDR4 DIMMs have a 72-bit bus consisting of 64 data bits and 8 ECC bits. In DDR5, each DIMM has two channels. Each channel is 40 bits wide, with 32 data bits and 8 ECC bits. Although the data width is the same (64 bits total), two smaller independent channels improve memory access efficiency. Therefore, using DDR5 not only increases speed, but also amplifies higher transfer rates through greater efficiency.
2.1.5 Longer burst length
The burst length of DDR4 is 4 or 8. For DDR5, the burst length will be extended to 8 and 16 to increase the burst payload. The burst length is 16 (BL16), allowing a single burst to access 64 bytes of data, which is a typical CPU cache line size. It does this using only one of two independent channels. This greatly improves concurrency and improves memory efficiency with two channels.
2.1.6 Larger capacity DRAM
DDR4 has a maximum capacity of 16 Gb DRAM in a single-chip package (SDP). The maximum capacity of DDR5's single-chip package can reach 64 Gb, and the capacity of the assembled DIMM has quadrupled to an astonishing 256 GB.
2.2 Challenges faced by DDR5 design
2.2.1 Using a separate full-rate clock, the clock rate corresponding to the 6400M T/s frequency is as high as 3.2GHz (it will support 8400M T/s in the future).
DDR5 DQS controls DQ read and write timing
The clock controls the command signal and the strobe signal controls the data. The requirements for clock signal jitter are more stringent, and the timing requirements for various command signals, data and address signals are also higher.
2.2.2 Bidirectional multiplexed data bus, time-sharing multiplexed link for reading and writing data.
Because resource read and write operations such as limited link channels and layout space continue to use the shared bus, time-sharing operations are required. From a verification testing perspective, it is also necessary to separate the read and write signals separately to check whether they meet the specifications.
DDR5 read and write shared bus
2.2.3 Burst DQS and DQ signals bring more ISI effect problems when transmitting on limited-bandwidth links in the context of higher rates.
Reading and writing the leading bit in DQS, the first bit of the burst, etc. all have different effects and performances. In addition, considering that the design of memory circuits is different from that of serial circuits, there are more impedance mismatches, so the ISI caused by reflection problems or interference will be more serious.
DDR5 uses more high-speed serial bus-like signal processing at the receiving end.
Therefore, when the receiving side rate is greater than 3600MT/s, the mature DFE equalization technology similar to high-speed serial circuits and standard buses is used. The variable gain amplification (VGA) is configured through the MR register to compensate for the link when transmitting at a higher rate. losses on. CTLE used in the DDR4 standard is a commonly used linear equalization amplification. Although it is simple and easy to implement, its by-product of amplifying noise is also more common. Considering the reflection-to-noise ratio in the DDR5 bus, it is not used. In addition, the definition and analysis of signal jitter such as crosstalk and reflection of parallel buses will also change accordingly.
From a testing perspective, the oscilloscope cannot obtain the signal at point TP2, which is the equalized signal, but can only obtain the signal at point TP1. The signal is then equalized through the equalization algorithm in the analysis software integrated on the oscilloscope to obtain an open signal. eye diagram. The reference clock for eye diagram analysis comes from the DQS signal based on the clock signal. In addition, the eye diagram test has been expanded from only DQ in the past to include CMD/ADDR bus.
3. New testing methods for DDR5
3.1 Transmitter TX test challenge
3.1.1 Separation of reading and writing
Since the specification stipulates DDR5, there is no longer a strict phase difference between reading and writing at the pins like traditional DDR. Therefore, the traditional method of using DQS-DQ phase difference and pre-signal mode may no longer be applicable, and new methods need to be used to separate read and write data.
According to the truth table, it can be seen that CA4 has different logic levels during read and write operations, so read and write separation can be performed based on the state of CA4 in combination with read and write delays.
3.1.2 New test parameters
As rates increase, new test parameters may be needed to identify critical signals. Jitter becomes an important component of critical signals. The specification defines a completely new definition of UI jitter.
And the measurement algorithm for this UI.
The measurement items of the UI will cover CLK(input), DQS(tx) and DQ(tx) signals, and the requirements are very strict.
According to the calculation in the table below, taking the rate of DDR5 4800 as an example, the maximum measured value of Rj is required to be 0.0037UI, which is 769.6fs.
Such demanding measurement results also place very high requirements on the performance of the instrument itself. The calculation formula of the instrument's jitter measurement background is as follows. It can be seen that the oscilloscope's background noise and background jitter have a great impact on the jitter measurement.
Keysight's UXR flagship real-time oscilloscope has an extremely low jitter of 25fs and a noise floor of 165μV (rms) (under 16G bandwidth). Can provide reliable DDR5 related jitter testing.
3.1.3 Test methods
The TX measurement method of DDR has always been what we are concerned about. Before DDR4, the test points specified by the specification were all at the DRAM ball. In DDR5, except for the eye diagram test, no additional updates have been made to other test points.
We recommend using the interposer method for measurement, as shown in the figure below.
After the measurement is completed, the waveform conversion from the actual measurement point to the theoretical test point is realized through mathematical calculation of S parameters.
For DDR5 eye diagram testing, if the DFE function is turned on, the oscilloscope can further complete the equalization operation on the basis of de-embedding, and finally obtain the required waveform.
Of course, Keysight has provided automated testing apps to conveniently provide users with visual one-click testing solutions.
3.1.4 New scenarios for controller testing
As the signal rate continues to increase, controllers, links, and chips have joined the testing army. The figure below shows the TX test scenario for the controller and PCB interconnection link. Through the use of an oscilloscope and a fixture, the signal quality test of the transmitter is realized.
3.2 Receiver RX test challenge
3.2.1 New technologies at the receiving end
In previous high-speed serial link designs, we know that as the rate continues to increase, link loss and ISI have an increasing impact on high-frequency components. Therefore, in PCIE Gen3, receiver equalization was introduced The concept is used to compensate for the loss of high-frequency components.
Specifically, there are the following points. ① The signal at the receiving end will first be equalized by CTLE (continuous time linear equalization). The figure shows the CTLE curve with 7 DC gains. Then the signal will be divided into two, and one part is given to CDR②. The OJTF function of the core PLL in CDR is a high-pass filter similar to the one on the left. The other part of the signal will give ③ DFE (decision feedback equalization) with one tap.
We pay special attention to the two test points identified in the picture, one is TP2 and the other is TP2`. Usually TP2 uses signals actually captured by an oscilloscope, while TP2` uses a standard reference receiver model to restore the waveform actually seen by the chip. So does this equalization technology have any reference significance for DDR5?
First, let’s take a look at what is special about DDR5 compared to traditional serdes technology.
full rate clock
There is no PLL at the receiving end
single ended signal
There are so many that not only the impact of loss must be considered, but also the impact of crosstalk.
Multi-particle application scenarios, each particle is independently trained and balanced
In addition to understanding several special features of DDR5 and traditional Serdes, I made some adjustments with reference to the equalization technology used on PCIE as follows.
The first is CDR. Since there is a display clock in the system, a DLL module without frequency tracking capability can be used to replace the original complex CDR module. The second one is CTLE. Although CTLE is simple to implement, considering the reflection and crosstalk in the single-ended DDR5 bus, it seriously deteriorates the signal-to-noise ratio, so a VGA variable gain amplifier is used instead of CTLE. The third one is based on the mature DFE equalization technology. The last one follows the previous write leveling and read leveling mechanisms of DDR. The de-emphasis function originally implemented on the receiving end is implemented on the controller end.
3.2.2 New challenges in receiver testing
The purpose of the traditional Serdes receiving end test (taking PCIe as an example) is to determine whether the DUT can reliably receive signals with specified damage at the ball of the chip package (or the gold finger of the CEM specification) and achieve the required bit error rate. Require.
For DDR single-ended parallel bus systems, non-correlated jitter, level interference, ISI, crosstalk, and reflection are crucial to the reliable operation of the system. The DDR5 receiver test not only includes the stress eye test, which is to meet specific bit error rate requirements under a given stress eye signal, but also includes sensitivity tests in terms of amplitude voltage and horizontal jitter.
The DUT under test can be a controller, DRAM, buffer/register, DIMM, etc.
3.2.3 New methods for receiver testing
The specification defines all test point requirements in the receiver test, as well as the waveform specification requirements after the equalizer. Before testing, it needs to be calibrated according to the requirements of the specification.
Before calibrating, take into account the special characteristics of the DDR bus. ODT will be used to optimize the signal quality from the transmitter to the receiver. Since it allows different impedance settings, it is recommended to use 48 ohms for calibration during the receiver test to minimize mismatch with standard test equipment. Under this assumption, the pressure signal is generated by adjusting the shape of the signal through the BERT settings of level and jitter.
Keysight provides DDR5 receiver test solutions based on the M8000 series bit error analyzers, supporting testing of controllers, DRAM, buffers/registers, and DIMMs.
3.2.4 Calibration of receiver test
The figure below shows the topology of DDR actually used in system products. From the DDR controller, through the PCB path, to the DRAM particles on the DIMM.
When doing calibration, we also refer to the topology in the above figure to complete the simulation of the entire path. For DIMMs or particles, the signal is sent by BERT, passes through CTC2 Board and replicate card, and is finally received by the oscilloscope to form a complete end-to-end link.
What should be noted here is that there are corresponding fixtures for different product tests. The main clamps are as follows. They are the C2C test card, System Motherboard Test Fixture, and Device Validation Fixture in the picture below.
Among them, the CTC2 test card provides a DIMM socket, and at the same time, all signals on the DIMM, including CA/CMD, DQS, and DQ, are led out through SMP connectors. Used for calibration and testing of DIMM, RCD test fixtures, Data Buffer test fixtures, DRAM test fixtures, etc.
CTC2 test card
System Motherboard Test Fixture also extracts CA/CMD, DQS, and DQ signals through SMP for transmitter testing of the controller and receiver test calibration and testing of the controller. It also supports the channel characteristics of the system motherboard. verify.
System Motherboard Test Fixture
Device Validation Fixture includes RCD test fixtures, Data Buffer test fixtures, DRAM test fixtures, and Combo test fixtures, etc. Mainly used for calibration and testing of single device products, as well as calibration and testing of multiple devices. Insert it into the test card of CTC2 during testing.
Device Validation Fixture
The figure below shows the calibration operation based on the CTC2 test card. The connection method is shown in the figure.
Use the M80885RCA automation software and follow the wizard to complete the setup of the test environment parameters and initialize the DUT.
Step by step, realize automatic calibration of each parameter of DQS&DQ and CK&CA. After completing the automated calibration, you can view the test results of each calibration item, as shown in the figure below.
3.2.5 Receiver test
The receiving end test includes two parts of the test content, the Sensitivity test and the Stressed Eye test. The Sensitivity test includes Voltage Sensitivity and Jitter Sensitivity.
In the Voltage Sensitivity test of DQS and DQ, keep the DQ signal unchanged when testing DQS, and keep the DQS signal unchanged when testing DQ. Continuously adjust the variable of another parameter, and after traversing the entire parameter range, count the bit error rate.
In the Jitter Sensitivity test of DQS, clean clk and dq are first output. On this basis, the phases of DQS and DQ are traversed to calculate the sensitivity test of the background jitter. Then change the combination of DCD and Rj and DCD and Rj in sequence, traverse the phases of DQS and DQ, and complete the jitter Sensitivity test in various scenarios.
In the Stressed Eye test, the stress signal during the calibration process (as shown below) is used to perform the loopback bit error rate test.
After the test is completed, the M80885 consistency software will provide the test results and test report on the right side of the picture above.
Keysight Technologies can bring you complete end-to-end solutions. Including simulation in the early stage of design, covering modeling by memory designer and pre- and post-ADS simulation. For transmitter testing, we provide UXR real-time oscilloscopes with industry-leading performance indicators and high-performance RC model probes to effectively reduce test load. For receiver testing, we provide the all-in-box M8000 series bit error analyzer, which supports receiver calibration and testing of controllers, DRAM, Data Buffers, RCDs, and DIMMs. In terms of protocol analyzers, the U4164A series supports complete DDR and LPDDR protocol decoding tests.
Review Editor: Huang Fei
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