Agile Analog launches first full RISC-V analog IP subsystem at RISC-V Summit Europe

Cambridge, UK, 5 June 2023. Agile Analog, the customizable analog IP firm, is launching the primary full analog IP subsystem for RISC-V purposes on the RISC-V Summit Europe in Barcelona (5-9 June). The preliminary subsystem contains all of the analog IP required for a typical battery powered IoT system, together with an influence administration unit (PMU), a sleep administration unit (SMU), and knowledge converters. This distinctive, course of agnostic, customizable and digitally wrapped analog IP subsystem will assist resolve lots of the points that System on Chip (SoC) designers at present encounter, because it pairs with a RISC-V core to kind an entire answer.

Chris Morrison, Director of Product Advertising at Agile Analog, explains:

“The RISC-V structure is enabling a surge of recent SoC product developments, and the demand for extra accessible and configurable IP options is growing. One of many main challenges that digital chip designers face is in integrating the analog circuitry to assist their SoC designs.”

Chris provides: “With our RISC-V analog IP subsystem, it’s potential to entry the suitable analog IP for a particular course of and foundry. This will then be built-in seamlessly with digital IP from a digital IP supplier within the RISC-V area, simplifying chip design and accelerating the time to marketplace for new RISC-V IoT purposes. As with all the Agile Analog IP, this subsystem is customizable to provide the precise function set required for the applying.”

Conventional analog IP has been a serious bottleneck for a few years, with restricted choices obtainable, and chip designers have struggled to combine a number of analog IP blocks, typically from a number of distributors. The design and verification of the mixed-signal boundary between analog and digital has been a very daunting activity, as that is famend for being time-consuming and costly, requiring specialist data and instruments. Nonetheless, because of Agile Analog’s distinctive know-how and novel digitally wrapped strategy, these integration and verification challenges will be addressed and promptly resolved by Agile Analog on behalf of the shopper.

This new analog IP subsystem is verified in each analog and digital environments, connects on to the MCU’s peripheral bus, and is equipped with a SystemVerilog mannequin for straightforward integration into an SoC’s current digital verification atmosphere.

Calista Redmond, CEO of RISC-V Worldwide, feedback:

“RISC-V is already seen in over 10 billion cores globally, and the RISC-V ecosystem is flourishing. It’s actually vital that there are modern options like this to assist chip designers in our group to fast-track the supply of thrilling new RISC-V IoT purposes.”

Agile Analog can be exhibiting and presenting on the RISC-V Summit Europe 2023.

Agile Analog’s preliminary RISC-V subsystem macro for IoT purposes is out there now consisting of the next sub-blocks:

agilePMU

The agilePMU Subsystem is an environment friendly and extremely built-in energy administration unit for SoCs/ASICs. That includes a power-on-reset, a number of low drop-out regulators, and an related reference generator, that is designed to make sure low energy consumption whereas offering optimum energy administration capabilities. Geared up with an built-in digital controller, this subsystem presents exact management over start-up and shutdown, helps provide sequencing, and permits for particular person programmable output voltage for every LDO. Standing displays present real-time suggestions on the present state of the subsystem, making certain optimum system efficiency.

agileSMU

The agileSMU Subsystem is a low energy built-in macro consisting of the important IP blocks required to securely handle waking up a SoC from sleep mode.  Sometimes containing a programmable oscillator for low frequency SoC operation and RTC, quite a few low energy comparators which can be utilized to provoke the wake-up sequence, and a power-on-reset which supplies a strong, start-up reset to the SoC. Geared up with an built-in digital controller, this subsystem presents exact management over wake-up instructions and sequencing. Standing displays present real-time suggestions on the present state of the subsystem, making certain optimum system efficiency over the total product lifecycle.

agileSensorIF

The agileSensorIF Subsystem is a low energy built-in macro offering all of the analog required to interface with exterior sensors. That includes two up-to 12-bit and 64 MSPS SAR ADCs, a 12-bit DAC and a number of programmable comparators, this sensor interface supplies all of the connections wanted to interface with the surface world. Built-in programmable acquire amplifiers and buffers assist a variety of exterior sensors and programs. It's outfitted with an built-in digital controller and standing displays to offer real-time suggestions on the present state of the subsystem, making certain optimum system efficiency over the total product lifecycle.

Agile Analog firm profile:

Agile Analog™ is remodeling the world of analog IP with Composa™, its modern, configurable, multi-process analog IP know-how. Headquartered in Cambridge, UK, with a rising variety of companions and clients throughout the globe, Agile Analog has developed a singular approach to mechanically generate analog IP that meet the shopper’s precise specs on nearly any course of from any foundry. The corporate supplies a large and ever-expanding collection of analog IP and subsystems for energy administration, knowledge conversion, IC well being and monitoring, safety, and always-on domains. Agile Analog’s novel strategy makes use of tried and examined analog circuits inside its Composa library to create personalized and verified analog IP options. This reduces the time to market and will increase high quality, serving to to speed up innovation in semiconductor design. www.agileanalog.com