An article explaining the working principle of RCD buffer circuit in detail
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# An article explaining the working principle of RCD buffer circuit in detail

Posted Date: 2024-01-20

In actual SMPS testing, voltage spikes and oscillation waveforms are always seen. What are the potential hazards of voltage spikes and oscillation waveforms? Voltage spikes can cause devices to exceed voltage limits and be damaged, while also causing circuit EMI performance degradation.

Snubber circuits reduce voltage spikes, suppress oscillations, and protect devices.

Where do voltage spikes and oscillations come from? Inductive devices and capacitive devices coexist in a circuit. In fact, parasitic inductance and parasitic capacitance are inevitable. When the damping coefficient is less than 1, the resistive component of the circuit cannot effectively suppress the energy exchange between the inductor and capacitor. When When an excitation event occurs, it is equivalent to the switch state transition shown in the figure.

In Figure 1, when the switch state changes, the capacitor voltage changes to this level. In Figure 2, when the switch state changes and the capacitor voltage reaches this level, when the capacitor reaches its first peak voltage, it begins to return energy back to the inductor and voltage source. Electrical energy is then transferred between the inductor (voltage source) and the capacitor, and oscillations result.

How to limit the peak voltage in Figure 1 and suppress oscillation? By freewheeling the current in the inductor with a larger capacitor, the inductor peak voltage can be reduced. For example, with a 16uH inductor and an initial current of 2A, feeding a 256pF capacitor, the peak voltage will be 500V. In the picture on the right, increase With a diode and a larger 10nF capacitor, the peak voltage can be reduced to 213.3V at an initial voltage of 200V. This is how the RCD snubber circuit works.

Generally, there are two snubber circuits in the flyback switch. One is the RCD snubber circuit, which is used to clamp the peak voltage of the flyback primary-side MOSFET when the MOSFET is turned off. The other is the RC snubber circuit, which is used when the MOSFET is turned on. , limiting the peak voltage of the rectifier diode and reducing the oscillation amplitude.

In the example below, the snubber circuit test data is based on an evaluation board with the following parameters. 7.2W flyback converter, the input is 90~264Vac, the output voltage is 12V, the maximum current is 0.6A, when testing the peak drain-source voltage (Vds) waveform, the input used is 220Vac, the output resistance is 25R, and the output current is 0.48A . When using the RCD buffer circuit, the peak drain-source voltage is 452V. After removing the RCD, Vds is 513V, indicating that the RCD circuit can reduce the voltage spike by 61V.

How to determine the design parameters of Rsn, Csn and Dsn?

The RCD snubber circuit actually transfers the electric energy stored in the leakage inductance to the snubber capacitor (Csn) and dissipates the electric energy through Rsn.

MOSFET peak current (Ipk) and switching frequency are determined according to power supply design requirements.

When designing the RCD snubber circuit, pre-set the snubber capacitor voltage (Vcsn) and reflected voltage (VR). When VR is the reflected voltage of the secondary output winding through the turns ratio of the transformer.

When the MOSFET is turned off, the Lk current maintains the initial direction, ignoring the current flowing to Coss. Assume that all current flows to Csn, which is equivalent to the inductor being connected in series with the voltage source to charge the capacitor. Therefore, the discharge time of the leakage inductance can be calculated from Formula 1. Calculate the charging power of Lk to Csn from Formula 2. The electric energy entering the capacitor will be consumed by the resistor Rsn, which can be calculated by Formula 3.

Tsw is the switching cycle duration, fsw is the switching frequency.

In flyback, the critical duty cycle is as follows. Generally speaking, the maximum duty cycle is around 70%. For the common DC input voltage range of 80~375V, the reflected voltage range is 60~120V. When calculating Vcsn, use the following The formula sets K and Prsn.

The picture on the right shows the relationship between Psn/Plk and K and Vds and K. The larger K is, the smaller the loss of Rsn is and the higher Vds is. Vcs_max depends on the maximum input voltage, MOSFET withstand voltage and MOSFET voltage margin.

For example, Vin_max=375V, using 700V MOSFET, Vmar=100V, then VCsn_max is 225V. Considering VCsn and Prs at the same time, it is generally recommended that the K value ratio is between 1.5~3n. Using the formula of k, VCsn is 225 and Vr=75V, which is The design chooses k as 3 to achieve higher efficiency.

After determining VCsn and Vr, calculate the value of Rsn through Equation 4, and select the minimum acceptable Csn(Vl) value after discharge in one switching cycle. VL should always be higher than (Vin+Vr), and VH is the initial value of Vcsn.

The discharge time is approximately equal to the switching time (Tsw). The Vc rising curve is a small fraction of the overall RC discharge curve. This is the derivation of the Csn curve calculation formula.

Dsn uses a fast diode. Note that the withstand voltage of the diode must be greater than or equal to the withstand voltage of the MOSFET. A 1A diode can meet at least 100W flyback. Because the forward conduction time of Dsn is very short, only a few hundred nanoseconds. The highlighted area on the left is enlarged as shown on the right. The reverse recovery characteristics of Dsn have a significant impact on the Vds peak voltage and oscillation, as shown in the measured waveform. , after the inductor charges Csn, a voltage drop occurs in Vcsn, which is due to the reverse recovery of Dsn. During the recovery time of Dsn, Csn will release part of the electric energy. After that, Vds is less than (Vin+Vcsn), and Lk and Coss will resonate. For a short period of time, under normal circumstances, a Dsn with a Trr of 500nS can meet tens of watts of flyback power. If the switching frequency is high and the heat dissipation conditions are poor, ultra-fast diodes should be used, and Trr should be less than 100nS.

For Dsn, use slow tube. Note that the highlighted area on the left is enlarged, as shown in the picture on the right. If a slow diode is used, Trr is about 1.5uS, and Csn will transfer more power to the secondary side. Therefore, the Vcsn drop is much larger than that of a fast diode. The reverse current of a slow diode is very soft and therefore the subsequent oscillation is small. However, the slow tube is only suitable for low power, and it is recommended to be less than 10W. Because the slow tube will bear more power consumption, the temperature inside Dsn will be higher.

On the flyback secondary side, when the MOSFET is turned on, the initial value of the secondary voltage Vsec is between (-Vout) and (+Vout). Here, the initial secondary i voltage Vsec_ini is equal to +Vout as the worst case for analysis. When the MOSFET turns on the device, the voltage of C will reach (Vout+Vin/n). In this process, its amplitude reduction effect can reduce the voltage spike of the diode.

First let's look at how increasing or decreasing the capacitance and resistance values ​​affects the transients. When R remains unchanged, the higher the capacitance, the smaller the voltage undershoot and the smoother transition to a stable state. However, the higher the capacitance, the greater the power consumption. When C remains constant, the resistance value is optimal and the minimum undershoot voltage can be achieved. Higher or lower resistance will increase the undershoot voltage.

To simplify the calculation, we decompose the circuit with RC buffer into two second-order circuits and analyze them respectively. Short-circuit C to obtain circuit 1. The no-oscillation condition of this circuit is as shown on the right. Disconnect Cd to obtain circuit 2. The no-oscillation condition of this circuit is also as shown on the right.

Learn more about the impact of the relationship between C and Cd on 2 second-order circuits. Let C equal m*Cd. If R can satisfy the following inequality, then the two circuits can satisfy the no-oscillation condition at the same time. It can also be represented by a graph. The horizontal axis is m, and the vertical axis is the ratio of Rcr_2 and Rcr_1. When the Y-axis ≤ 1, m ≥ 16.2 circuits all meet the no-oscillation condition. However, in practical applications, when C is 16 times Cd, it will cause higher losses. While satisfying efficiency, it is necessary to comprehensively consider reducing the limit of undershoot or oscillation. Generally speaking, m is acceptable when it is between 2.5 and 10.

In practical applications, C=m*Cd, m is usually 2.5~10. Therefore, if the frequency of circuit 1 is calculated using this formula, the natural frequencies of the two circuits have the following relationship. If Wn1>Wn2, the peak voltage of circuit 1 comes earlier than that of circuit 2. Due to power consumption, m cannot reach 16, so we need to determine which circuit is the main cause of the peak voltage. For this purpose, we make a practical flyback case to determine RC.

Determine RC through the following 6 steps:

Measure the Vcd oscillation frequency without RC circuit when the MOSFET is turned on. As shown in the waveform, the frequency is 40MHz;

Make R=0, choose an appropriate capacitor, and reduce the frequency by about half. As shown in the waveform, select C=470pF, and the frequency is about 13MHz;

Calculate the values ​​of Cd and Lk. Cd=64p, Lk=266nH. (This is because the frequency is approximate, so it should be calculated according to the actual test, for reference only)

Calculate the power loss of R: The power loss of R is actually the loss in the resistor caused by the charge and discharge of the capacitor C. This formula is used here to calculate the charge and discharge loss. The total loss of R is as follows. For example, C=470,560,820pF power loss. In addition, it is necessary to use a resistor with a power rating more than twice that of Pr.

Calculate the critical damping Rcr_1 and Rcr_2. To calculate lower losses, use a 470pF capacitor and use the combination of RC=33R, 470pF. , and RC=47R,470pF combination to test the results. Vin=220V, Iout=0.48A, as shown on the right, the resistor has a good effect on oscillation suppression. The results show that circuit 2 is the main cause of the peak voltage, but this does not mean that 47R is the final choice. There are other circumstances to consider.

When the circuit enters CCM mode, the rectifier diode reverse recovery occurs, causing Lk to have a high initial current, causing the Vd voltage to spike.

It can be seen that C=470pF, and Iout=0.48A remain unchanged. When R decreases, the peak voltage increases, making circuit 2 the main cause of the peak voltage. However, the worst case scenario is when the output is shorted and Lk carries the highest initial current. These waveforms show the same capacitance and falling R, but the output is not shorted. When the output is short-circuited and R drops, the peak voltage drops. Making circuit 1 the main cause of the peak voltage. Therefore, adding a high Rsn will reduce the power entering circuit 2, possibly causing circuit 1 to become the main cause of voltage spikes. Therefore, in CCM, it is necessary to reduce Rsn to reduce the peak voltage.

Keep R constant and adjust C. Under normal operation and output short circuit conditions, large capacitance can reduce the peak voltage, but it will increase power consumption. As shown in the waveform, after C rises to a certain level, the amplitude of the peak voltage will decrease slowly.

Finally, the appropriate RC combination should be selected based on power consumption, peak voltage, and EMI performance.

Review Editor: Huang Fei

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