# Anti-aliasing filter component selection for delta-sigma ADC analog-to-digital converters

QA&Q: Anti-aliasing filter component selection for delta-sigma ADC analog-to-digital converter

Low-speed delta-sigma ADCs typically require a simple single-pole RC filter to reduce aliasing effects. For differential signals, the filter structure usually consists of two filter paths: a differential filter (derived from the combination of two filter resistors RFILTER and differential capacitor CDIFF); and a common-mode filter (derived from a filter resistor RFILTER and common mode capacitor CCM). This is shown in Figure 1.

Figure 1: Anti-aliasing filter structure for low-speed delta-sigma ADC

(Note: If you have a single-ended input where AINN is the ground reference, the filter will consist of RFILTER and CCM. However, the design guidelines will be the same as for a differential filter described below.)

To determine the value of each component in Figure 1, it helps to divide the analysis into three parts:

What should the differential filter cutoff frequency be?

What value of filter resistor should I choose?

What value of differential and common mode capacitors should I choose?

For each problem, the ADS124S08 (24-bit, 12-channel, 4kSPS delta-sigma ADC) will be used as an example data converter to help illustrate how to put these design principles into practice.

What should the differential filter cutoff frequency be?

The purpose of the anti-aliasing filter is to keep the frequency content at or near the ADC modulator frequency (fMOD) so that it no longer aliases the return passband because these frequencies are not rejected by the digital filter itself. Therefore, set the 3dB cutoff frequency fC-DIFF of the differential filter so that it is 10 to 100 times lower than fMOD. This will result in 20dB to 40dB frequency suppression around fMOD respectively. The amount of suppression required depends on the design goals of the system. If you want to learn more about the basics of anti-aliasing filters and why you should be concerned about modulator frequency aliasing.

For the ADS124S08, fMOD is fCLK/16, where fCLK is the master clock frequency, as shown in Figure 2. Given a nominal internal oscillator frequency of 4.096MHz, fMOD = 4.096MHz/16 =256kHz. Therefore, for this particular ADC, one can choose fC-DIFF = 2.56kHz or fC-DIFF = 25.6kHz to obtain 20dB or 40dB rejection respectively. In addition, please ensure that fC-DIFF is also greater than the -3dB frequency f3dB of the digital filter, otherwise the RC filter will affect the digital filter characteristics.

Figure 2: ADS124S08 digital filter structure and modulator clock

What value of filter resistor should I choose?

In the system shown in Figure 1, the filter resistor also acts as a current limiter. Therefore, the size of this resistor limits the maximum pin input current (IMAX) as shown in the ADC's Absolute Maximum Ratings table. To determine the allowable voltage drop across this resistor, you need to see the expected overvoltage condition at the system input (VOV) and the turn-on voltage of the ADC's integrated ESD protection diode (VESD). You can then use the following formula to solve for the resistor value RFILTER:

RFILTER >(VOV – VESD)/IMAX

For the ADS124S08, IMAX is 10mA. As shown in Figure 3, when the input voltage exceeds the analog power supply by 300mV, the ESD diode of the ADS124S08 will conduct.

Figure 3: ESD information of ADS124S08

If you assume AVDD = 5V, and the expected maximum overvoltage condition VOV is 20V, you now have all the information you need to determine the minimum resistance value of RFILTER:

VOV =20V

VESD =AVDD + 0.3V = 5.3V

IMAX =10mA

RFILTER >(VOV – VESD)/IMAX =(20V – 5.3V)/10mA =1,470 Ω

Note that this is the absolute minimum value that the resistor can be used to limit the current into the ADC pin, given the system parameters. It is good practice to allow some margin for overvoltage conditions and maximum current when calculating resistor values. This ensures a more robust protection circuit to accommodate any potential system changes. For example, you could assume a 10% tolerance for VOV and a 30% tolerance for IMAX:

VOV =VOV x 1.1 = 22V

VESD =AVDD + 0.3V = 5.3V

IMAX =IMAX x 0.7 = 7mA

RFILTER >(VOV – VESD)/IMAX =(22V – 5.3V)/7mA = 2,386Ω

After calculating the appropriate resistor value, select a standard resistor that is equal to or greater than that value.

What value of differential and common mode capacitors should I choose?

Since you have already determined the filter cutoff and resistor values, you can use the following formula to determine the capacitance of the differential filter CDIFF:

CDIFF =1/(2 x π x fC x(2 x RFILTER))

Then choose the common mode capacitor CCM so that it is 10 to 20 times smaller than CDIFF, so:

CCM =CDIFF/10

Given the previously determined RFILTER and fC-DIFF values, you can calculate the capacitor value as follows:

CDIFF =1/(2 x π fC x(2 x RFILTER)) = 1/(2 x π x 2,560Hz x (2 x 1,470Ω)) = 21nF

CCM =CDIFF /10 = 21nF/10 = 2.1nF

Review Editor: Tang Zihong

#Antialiasing #filter #component #selection #deltasigma #ADC #analogtodigital #converters

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