CEA-Leti and Intel put 2D materials on 300mm wafers for nano-sheet transistors

The goal of the multi-year mission is to develop a approach to switch layers of second materials, grown on substrates as much as 300mm, to a second substrate for Transistor constructing. Intel will provide manufacturing experience and CEA-Leti has bonding, layer-transfer and characterisation information.

“Attributable to their development temperature exceeding 700°C, and development on most well-liked substrates, 2D supplies can hardly be deposited on a stack as skinny layers, so switch holds essentially the most promise for integrating them,” stated CEA-Leti CEO Sebastien Dauvé (photograph left).

Sub-nm mosfets

The intention is to construct substrates with which to make sub-1nm channel-thickness stacked-nanosheet fets – one of many applied sciences mooted as a successor to CMOS.

“Molybdenum and tungsten-based transition-metal dichalcogenides are promising candidates to make sure scaling of mosfets,” based on CEA-Leti. “They're appropriate for high-performance and low-power platforms on account of their good provider transport and mobility, even for atomically skinny layers. As well as, their machine physique thickness and average power bandgap result in enhanced electrostatic management and, thus, to low off-state currents.”

“2D TMD materials is a promising possibility for extending the boundaries of transistor scaling sooner or later,” stated Intel’s European director of analysis Robert Chau (photograph proper).

Based in 1967, CEA-Leti is a world-leading Semiconductor analysis lab with 1,900 workers in Grenoble. It has workplaces in Silicon Valley and Tokyo, and has launched 76 start-ups.

View extra : IGBT modules | LCD displays | Electronic Components