Comprehensive understanding of various features of RISC-V and ARM
RISC-V and ARM are two processor architectures that have attracted much attention in recent years. RISC-V is an open source instruction set architecture (ISA) based on reduced instruction set computing (RISC) principles, while ARM is a proprietary ISA that has long dominated embedded systems and mobile devices.
This article will explore the history, architectural features, performance, power consumption, ecosystem and future prospects of RISC-V and ARM in detail to gain a more comprehensive understanding of the characteristics of RISC-V and ARM in various aspects.
01. What is ISA (Instruction Set Architecture)?
At the heart of every processor's functionality lies its instruction set architecture (ISA), which specifies the set of instructions that the processor can understand and execute. It acts as the basic bridge between hardware and software and determines the functionality and performance of the processor. The choice of ISA directly affects how software is developed and has long-term effects on the efficiency, compatibility, and flexibility of the processor.
ISAs can be broadly divided into two types: open and closed. Closed ISAs, like ARM, are proprietary and tightly controlled by a specific company, provide a given level of reliability and compatibility, and limit customization. In contrast, open ISAs represented by RISC-V are community-driven, provide greater flexibility in customization, and can promote innovation and adapt to specific needs.
The comparison between RISC-V and ARM mainly revolves around the different ISAs they use, each with different advantages and methods to meet changing computing needs.
02. RISC-V and ARM: background and history
Historically, the x86 architecture has dominated and promoted the development of giants such as Intel, but with the emergence of ARM, the story has opened a new chapter.
ARM originated from Acorn Computers, a British company that developed the Acorn RISC machine architecture in the 1980s. The ARM architecture was originally designed for Acorn's personal computers, with a focus on power efficiency and simplicity. In 1990, Acorn Computers, Apple and VLSI Technology formed a joint venture called Advanced RISC Machines Ltd., which later evolved into ARM Holdings.
The first ARM processor, ARM1, was launched in 1985, followed by ARM2 in 1986. With Apple's Newton PDA (Newton personal digital assistant) selecting the ARM610 processor in 1993, the ARM architecture began to gradually appear in the public eye. , which also marked the beginning of ARM's dominance in the mobile and embedded systems markets.
Over the years, ARM has developed multiple processor families, each targeting specific market segments and performance requirements. Some representative ones include the Cortex-A series for high-performance applications, the Cortex-R series for real-time systems, and the Cortex-M series for microcontrollers and low-power devices.
ARM's success can be attributed to its innovative licensing model, which allows semiconductor companies to license ARM's IP and customize it to their specific needs. This flexibility allows multiple companies, including industry giants like AMD, to design and manufacture ARM-based CPUs and GPUs optimized for different applications. This has given rise to a huge ecosystem of ARM-based processors and devices. To date, ARM chip shipments have exceeded 180 billion, with approximately 30 billion ARM chips shipped every year.
The ARM architecture has become the de facto standard for mobile devices, the Internet of Things, and embedded systems, with products from major companies such as Apple, Samsung, and Qualcomm all relying on ARM processors.
Although ARM has achieved significant success in the market, it is a proprietary architecture that requires licensing fees and certain limitations in customization. This proprietary nature hinders use and development by small businesses, startups, and some researchers. RISC-V provides an open source alternative.
RISC-V originated in the Computer Science Department of the University of California, Berkeley. The project started in 2010 as a research effort led by Professors Krste Asanović, David Patterson and their team. The first RISC-V specification was released in 2011.
In 2015, the RISC-V International Organization was established to promote the adoption and standardization of the RISC-V ISA. The organization currently has more than 200 members, including major technology companies such as Google, Nvidia and Western Digital. RISC-V has been rapidly adopted in various industries, and many companies have launched RISC-V-based processors and systems on a chip (SoC).
One of the key milestones in the history of RISC-V was the 2017 release of the RISC-V Privileged Architecture specification, which defines the interface between hardware and operating systems. This specification promotes the development of more complex RISC-V processors and facilitates the porting of operating systems such as Linux to RISC-V platforms.
Another important milestone was the release in 2018 of the first commercial RISC-V processor, the SiFive Freedom U540. The processor demonstrates the feasibility of RISC-V in commercial applications, paving the way for further industry adoption of the architecture.
03. RISC-V and ARM: Architecture
RISC-V architecture block diagram
The RISC-V architecture is based on RISC principles and emphasizes the use of small, simple and efficient instruction sets.
Key architectural features of RISC-V include a load-store architecture, a fixed-length 32-bit instruction format, and a small number of general-purpose registers. RISC-V supports various integer instruction set extensions such as RV32I (32-bit), RV64I (64-bit), and RV128I (128-bit).
Here are some of the unique features of the RISC-V architecture:
Modularity and scalability: One of the hallmarks of RISC-V is its modularity and scalability. The ISA is designed to be easily extensible with custom instructions and coprocessors to enable custom needs. This flexibility is achieved through a modular design, whereby the basic ISA can be combined with optional standard extensions.
Compressed instruction set: Compared with ARM's Thumb instruction set, RISC-V also supports the RV32C (or RV64C) compressed instruction set extension, which provides 16-bit compressed instructions that can be mixed with standard 32-bit instructions. This feature helps reduce code size and improve energy efficiency, making RISC-V particularly advantageous for embedded systems and low-power applications.
Privilege levels and virtual memory: Another important aspect of the RISC-V architecture is its support for privilege levels and virtual memory. The RISC-V Privileged Architecture specification defines three privilege levels: machine mode (M mode), administrator mode (S mode), and user mode (U mode). These privilege levels provide a mechanism to isolate the operating system kernel, hypervisor, and user applications, ensuring system security and stability. RISC-V also supports a virtual memory system based on a multi-level page table scheme to achieve efficient memory management and protection.
ARM architecture block diagram
The ARM architecture is also based on RISC principles. Key architectural features of ARM include a load-store architecture, a mix of fixed-length 32-bit and variable-length Thumb instructions, and a large number of general-purpose registers. The memory system uses double-ended byte ordering, allowing ARM processors to seamlessly process and transfer data in both endian formats at the hardware level.
ARM processors are divided into multiple families, each targeting specific performance and power requirements. The most widely used ARM processor families are the Cortex-A, Cortex-R and Cortex-M families. The Cortex-A series is designed for high-performance applications such as smartphones, tablets and servers, supporting advanced features such as out-of-order execution, superscalar pipelines and hardware virtualization. The Cortex-R series is optimized for real-time systems, providing fast interrupt response times and deterministic behavior, and is commonly used in automotive, industrial and safety-critical applications. The Cortex-M series is tailored for microcontrollers and low-power devices with a focus on energy efficiency and ease of use.
Thumb instruction set: The Thumb instruction set provides 16-bit compressed instructions to increase code density and energy efficiency. ARM introduced the Thumb instruction set as an optional 16-bit extension to traditional 32-bit ARM instructions. This feature reduces code size while maintaining performance, making it suitable for memory-constrained devices such as embedded systems.
Memory management and protection: ARM processors support various levels of memory management and protection, including a Memory Protection Unit (MPU) for simple systems and a Memory Management Unit (MMU) for more complex systems with virtual memory support. The ARMv8-A architecture launched in 2011 added support for 64-bit address space, which provides a new 64-bit instruction set in addition to the existing 32-bit ARM and Thumb instruction sets.
Optional enhancements: In addition to the base ISA, ARM processors can include optional extensions such as NEON SIMD (Single Instruction, Multiple Data) for multimedia and signal processing tasks, and ciphers for hardware-accelerated encryption and decryption Learning, this allows ARM processors to efficiently handle a variety of workloads while maintaining low power consumption and a small chip footprint.
Overall, ARM has become an industry giant through its proprietary technology and comprehensive ecosystem, serving a variety of industries including mobile, embedded systems, and data centers. RISC-V is characterized by open source flexibility and adaptability, attracting users looking for customized solutions. Both architectures have their own advantages, depending on the actual needs of the user.
04. RISC-V and ARM: Performance
The comparison between RISC-V and ARM architectures is multifaceted and involves a range of factors that affect performance. Here are the comparisons between P550 and Cortex-A75 and BeagleV and Raspberry Pi.
ARM Cortex-A76 and SiFive P670 performance comparison
As shown, ARM's Cortex-A78 slightly outperforms SiFive's P670 (RISC-V) in peak single-thread performance, but the P670 has twice the compute density. So, given that SiFive's P670 processor is half the physical size of its competitors, its peak single-thread performance is comparable to the Cortex-A78.
It is worth noting that the Cortex-A78 was launched with the Vivo X60 and X60 Pro in December 2020, while the P670 was released on November 1, 2022, leaving a gap of nearly two years in research and development. ARM's latest processors now run on the ARMv9 ISA, which is a significant improvement over the Cortex-A78's ARMv8. The performance of the ARMv9 processor has been improved by about 30% and the energy efficiency has been improved by 50%.
In terms of pure performance, ARM processors maintain the lead. However, SiFive's P670 has twice the compute density of the Cortex-A78, putting RISC-V processors in a strong position in wearable technology.
In the performance comparison between RISC-V and ARM, ARM's iteration speed, complete ecosystem, and wide range of choices give it significant performance advantages. However, RISC-V’s modular nature and customization potential are more attractive for specific use cases. RISC-V developers also need to work hard to narrow the performance gap with ARM to gain a higher competitive advantage.
05. RISC-V and ARM: Power consumption
Since both architectures adopt a RISC philosophy, it is necessary to delve into the specific data and measurable factors that differentiate their power performance.
Power consumption is an important aspect of processor design, especially for embedded systems, IoT devices, and battery-powered applications. RISC-V's architecture emphasizes simplicity and modularity, which helps improve energy efficiency compared to more complex processor architectures. RISC-V ISA processors physically occupy less space, consume less power and are more energy-efficient.
RISC-V's fixed-length 32-bit instruction format simplifies decoding and reduces control logic complexity, thereby reducing power consumption. The optional RV32C (or RV64C) compressed instruction set extension provides 16-bit compressed instructions that can help reduce code size and improve energy efficiency by reducing instruction fetch and decode power. In addition, RISC-V's modular design allows some processors to be customized with only necessary functions based on specific application requirements, reducing power consumption by reducing unused hardware functions.
Such as the GreenWaves GAP8 processor for edge AI and machine learning applications. The GAP8 processor features a cluster of eight RISC-V cores and a dedicated convolutional neural network (CNN) hardware accelerator to achieve up to 200 GOPS/W (giga operations per second per watt) for AI workloads.
ARM's load-store architecture and a mix of fixed-length 32-bit and variable-length Thumb instructions simplify decoding and reduce control logic complexity, thereby reducing power consumption. In addition, ARM processors often include power management features such as Dynamic Voltage and Frequency Scaling (DVFS), which allows the processor to adjust its operating frequency and voltage based on workload demands, further improving energy efficiency.
ARM's processor families are designed with different power and performance goals in mind. For example, the Cortex-M series is optimized for microcontrollers and low-power devices with a focus on energy efficiency and ease of use. The Cortex-M4 processor runs at a frequency of up to 240 MHz and has a performance of 1.25 DMIPS/MHz. It includes hardware floating point unit (FPU) and DSP (digital signal processing) extensions, and is suitable for low-power signal processing and control applications. In the high-performance area, ARM processors such as the Cortex-A76 achieve excellent performance per watt and are ideal for power-constrained high-performance devices such as smartphones and laptops. The Cortex-A76 processor operates at up to 3 GHz, delivering peak performance of 4.0 DMIPS/MHz while maintaining low power consumption.
Overall, ARM's focus on power efficiency, coupled with its broad ecosystem and processor family, gives it a clear advantage when it comes to power efficiency. While RISC-V has a bright future due to its customization potential, its openness requires an investment of more time and resources to take full advantage of its energy-saving features.
06RISC-V vs. ARM: Ecosystem and Support
As an open source architecture, RISC-V has attracted a diverse community of developers, startups, and researchers. The RISC-V ecosystem is relatively young but growing rapidly. While it may not be as large as ARM, its openness promotes collaboration, customization and innovation. ARM already has a mature and broad ecosystem. Its licensing model has spawned a large number of ARM-based products.
Because RISC-V was born so short, related compilers, development tools, software development environments (IDEs) and other ecological elements are still developing. Currently, RISC-V has a full set of open source and free compilers, development tools and software development environments. This is a huge advantage of RISC-V. However, compared with ARM's commercial compilers and IDEs, the open source version still lags far behind. RISC-V must rely on strong commercial players for long-term support and promotion in order to achieve sustainable development.
In terms of hardware support, several semiconductor companies have developed RISC-V processors and systems on a chip (SoC), including SiFive, Andes Technology and Microchip. These companies offer RISC-V-based products ranging from low-power microcontrollers to high-performance application processors. In addition, the open source nature of RISC-V has led to the development of many open source processor designs, such as PULPino and RISC-V BOOM out-of-order superscalar processors. As Amazon and other tech giants explore the capabilities of RISC-V, the landscape of CPU architecture is shifting significantly, with open source hardware gaining ground.
On the software side, the RISC-V ecosystem supports a variety of operating systems, including Linux, FreeBSD, and real-time operating systems (RTOS) such as FreeRTOS and Zephyr.
Major semiconductor companies such as Qualcomm, Samsung and Apple have developed their own ARM-based processors to meet different market segments and performance requirements. These processors are used in a wide variety of devices, including smartphones, tablets, IoT devices, and embedded systems. On the software side, the ARM ecosystem supports operating systems such as Linux, Android, iOS and Windows, as well as real-time operating systems (RTOS) such as FreeRTOS and VxWorks.
06. What impact will RISC-V have on the development of China’s semiconductor industry?
In the long run, RISC-V will have epoch-making significance for China’s semiconductor industry, mainly in the following aspects:
Reduce dependence on foreign technology. RISC-V has gradually become a mainstream architecture and mainstream ecosystem. Through RISC-V, we can reduce our dependence on foreign technology and become more self-sufficient in the semiconductor industry.
RISC-V can drive innovation and differentiation. The open source nature of RISC-V also encourages innovation. By customizing the RISC-V core to meet specific needs, it will be relatively easy to develop new products and technologies based on RISC-V, which is usually more efficient than chips based on proprietary ISAs.
RISC-V can significantly reduce chip development costs. The RISC-V industry chain is becoming increasingly complete. From processor cores to hardware design, operating systems, development tools, benchmarks and solutions, the entire industry chain is complete, allowing the industry to share all costs equally.
In addition, the use of RISC-V can also help domestic companies develop new markets and applications for their chips. For example, RISC-V chips are ideally suited for use in IoT devices, edge computing and artificial intelligence applications, which are rapidly growing markets.
According to Semico Research’s forecast, by 2025, global RISC-V CPU core shipments will reach approximately 80 billion units, with a compound annual growth rate of 114.9%, accounting for more than 14% of global CPU core shipments. %. Other research data shows that the AI chip market based on RISC-V architecture will reach US$291 billion by 2027, with a compound annual growth rate of 73.6%; in the communication AI SoC market, RISC-V will maintain a growth rate of 21.2% from 2019 to 2027. % compound annual growth rate; in the data center market, the compound annual growth rate of the RISC-V CPU core market from 2021 to 2025 will be as high as 115%.
At present, significant progress has been made in the adoption of RISC-V architecture in China, which has had a certain impact on ARM's dominant position in the Chinese chip market. As RISC-V attracts more and more attention and applications around the world, it will gradually pose a competitive threat to ARM. It is expected that the future competition between RISC-V and ARM will promote the development of the entire chip industry in a more open, innovative and diversified direction.
Review Editor: Huang Fei
#Comprehensive #understanding #features #RISCV #ARM
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