# CoolSiC MOSFET M1H with excellent stability

**introduction**

Threshold voltage drift (VGS(th)) under practical application conditions has been a focus of SiC over the past few years.

Infineon was the first to discover the drift phenomenon of VGS(th) under long-term stress caused by dynamic operation and proposed a working gate voltage region aimed at minimizing drift over the service life. (1).

After continuous research and continuous optimization, the newly launched CoolSiC MOSFET M1H has been significantly improved in VGS(th) stability, and the drift effect is negligible in almost all cases.

**Symptom**

The VGS(th) drift phenomenon is typically characterized through high-temperature gate bias stress testing (DC-HTGS), which follows test guidelines defined by standards such as JEDEC.

Recent research results show that compared to the corresponding static gate stress test (DC-HTGS), including V_(GS(off))

Figure 1 shows the different effects under alternating current (AC) and direct current (DC) stress conditions. The data change in VGS(th) (ΔVth) is obtained using the maximum conditions in the data sheet (1).

Two different slopes can be seen in the figure. The first corresponds to the typical DC-like drift behavior ("DC fit"); the second, larger slope corresponds to the AC stress of the positive and negative power supplies. effect ("AC fit"), also known as gate switching instability (GSI).

Figure 1: Drift during continuous gate switching stress:

VGS,(on)=20V;VGS(off)=−10V;

Tvj,max=150°C and f=500kHz.(1)

**Our conclusion is:**Under stress conditions where the number of switching cycles exceeds 10⁸, AC drift is the main cause of stress; when the number of switching cycles is less, DC drift is the main cause of stress.

The data shows that switching stress causes VGS(th) to slowly increase over time. As the threshold voltage VGS(th) increases, an increase in channel resistance (Rch) can be observed. This phenomenon is described by equation (1), where L is the channel length, W is the channel width, μn is the electron mobility, Cox is the gate oxide capacitance, and VGS(on) is the on-state gate. The voltage, VGS(th), is the threshold voltage of the device (1).

The total RDS(on) is determined by the sum of the individual resistances, namely channel resistance (Rch), junction field effect transistor resistance (RJFET), epitaxial layer resistance in the drift region (Repi) and resistance of the highly doped SiC substrate (RSub). Equation (2) describes the entire composition of total RDS(on).

Therefore, an increase in VGS(th) will cause a slight increase in channel resistance, resulting in an increase in RDS(on) and conduction losses over time.**Gate switching stress**

To ensure and predict the long-term stability of the electrical parameters of our CoolSiC MOSFETs during typical switching operation, we developed and adopted a new stress test: the Gate Switch Stress Test (GSS). This test allows you to directly determine electrical parameter drifts that typically occur when operating in positive and negative drive voltage modes (positive V(GS,on): on; negative VGS(OFF): off). This test allows developers to quantify the new failure mechanisms mentioned above and is therefore necessary to qualify SiC MOSFETs.

GSS testing covers all important drift phenomena, including those that occur during normal device operation. Apart from the missing load current (which by itself does not change the drift behavior we observe) (3), we simulate the application as closely as possible by maintaining gate switching characteristics (e.g., voltage slope) similar to typical application conditions (see Figure 2)(1). To cover the potential effects of gate signal overshoot and undershoot, which are very common in real-world SiC MOSFET applications, we stress the maximum gate voltage and maximum quiescent junction temperature (Tvj,op) allowed by the datasheet. Realize the worst case scenario.

Figure 2: When frequency f=500kHz,

Typical GSS gate-source stress signal. (1)

Testing under worst-case conditions gives customers confidence that they can use the device over the entire specification range without exceeding drift limits. This approach therefore guarantees excellent device reliability while also facilitating the calculation of safety margins.

In addition to VGS(th), other parameters such as gate leakage current IGSS are also measured and are consistent across the hardware under test (1).

**Worst-case end-of-life drift assessment****and its impact on applications**

During the development of an inverter, a major task is to predict the service life of the equipment. Therefore, reliable models and information must be provided. After extensive testing under various operating conditions, we were able to develop a predictive semi-empirical model that describes the variation of threshold voltage with duty curve parameters such as: stress time (tS), gate Extreme bias low level (VGS(off)), gate bias high level (VGS(on)), switching frequency (fsw) and operating temperature (T) (ΔVGS(th) (tS,VGS(off) ,VGS(on),fsw,T))(3).

Based on this model, we established a method to evaluate the threshold voltage drift, using the worst-case end-of-life curve (EoAP) to calculate the relative R(DS(on)) drift. In the application, running at any frequency for a certain time, we can calculate the total number of switching cycles (NCcycle) before EoAP. Then, use NCycle to read out the relative RDS(on) drift.

The number of cycles depends on the switching frequency and operating time. Typical hard-switching industrial applications (e.g., solar string inverters) use switching frequencies of 16-50 kHz. Inverters using resonant topology typically have switching speeds in excess of 100kHz. The target life of these applications is usually 10-20 years, while the actual operating time is usually 50%-100%.

**The following example provides a sample evaluation:**

Target life (years): 20

Actual working time (%): 50%=>10 years

Actual working time (s): 315,360,000s (10 years)

Switching frequency (kHz): 48

Cycle duration (s): 1/switching frequency=0.0000208

Number of cycles at end of life =~1.52E+13

With an on-voltage of 18V, the relative change in RDS(on) is expected to be less than 6% at 25°C and less than 3% at 175°C, see Figure 3 (green dots in Figure 3).

Figure 3: Relative RDS(on) change at VGS(on)=18V, Tvj,op=25°C, 125°C and 175°C (2)

The Figure 4 example, based on the recently launched EasyPACK FS55MR12W1M1H_B11 (three-phase inverter bridge configuration in DC-AC inverter), illustrates the impact of changes in RDS(on) predictions (4). This example is an application where conduction losses (Pcon) account for a large proportion of the loss distribution. Tvj,op only rises 2K from the initial 148°C to the worst case EoAP of 150°C. The results prove that even after 20 years of use, the increase in Tvj,op caused by a slight change in RDS(on) is negligible.

Figure 4. Worst case EoL evaluation: Vdc: 800V, Irms: 18A, fout: 50Hz, fsw: 50kHz, cos(φ): 1, Th=80°C.

**Text in the picture:**

Power loss: power loss

Initial point：Initial point

Worst-case EoAP: Worst-case EoAP

This approach implies that the maximum drift should occur in the worst case scenario described. With the new M1H chip, customers will be able to choose the parameters most suitable for their application from the range of specifications in the data sheet. Parasitic overshoot and undershoot in the gate signal do not affect drift and need not be considered from an application perspective. Therefore, time and effort can be saved.

**Please note:**Applications running at well-controlled gate bias levels, well below the datasheet's maximum limits, e.g., +18V/-3V, will have even smaller changes in RDS(on) for the same number of switching cycles. .

**in conclusion**

We studied the threshold voltage characteristics under actual application conditions by conducting long-term tests under various switching conditions. We developed and implemented a stress testing procedure to determine worst-case EoAP parameter drift under realistic application switching conditions, providing our customers with a reliable predictive model.

In addition to other key improvements, Infineon's 1200V CoolSiC MOSFET, known as the M1H, shows excellent stability and reduces the effects of drift phenomena.

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**references**

(1) Infineon Application Note 2018-09

(2) P. Salmen, MW Feil, K. Waschneck, H.Reisinger, G. Rescher, T. Aichinger: A new test procedure to realistically evaluate the end-of-life electrical parameter stability of SiC MOSFETs in switching operation; 2021 IEEE International Reliability Physics Symposium (IRPS) (2021)

(3) Infineon: White Paper 08-2020: How Infineon controls and ensures the reliability of SiC-based power semiconductors, pp. 11–21;

(4) Data sheet FS55MR12W1M1H_B11

#CoolSiC #MOSFET #M1H #excellent #stability

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