Design Considerations and Challenges for SiC Power MOSFET Devices: Balancing Performance and Reliability
The idea of an acceptable gadget ought to enable a sure diploma of design flexibility to accommodate the necessities of assorted process situations with out the necessity for vital processing and format adjustments. Nonetheless, the important thing efficiency indicator stays the low particular on-resistance (R_DS(on)) of the chosen gadget idea, together with different listed parameters. Determine 1 presents some important parameters thought of, and extra parameters may be added.
Determine 1: Parameters to be balanced towards the efficiency indicators of SiC MOSFET (left) with the chosen parameters (proper)
One of many essential acceptance standards is the reliability of the gadget below its goal utility’s working circumstances. The first distinction from the prevailing silicon gadget world is that SiC elements function below increased inside electrical fields. Related mechanisms want cautious evaluation. Their widespread level is that the entire resistance of the gadget is outlined by the sequence connection of drain and supply contact resistances, together with extremely doped areas close to the contact, channel resistance, resistance of the JFET area, and drift area resistance (see Determine 2). Word that in high-voltage silicon MOSFETs, the drift area considerably dominates the entire resistance; in SiC gadgets, this element may be designed with considerably increased conductivity as described above.
Determine 2: Schematic of planar DMOS SiC MOSFET (left) and vertical trench TMOS SiC MOSFET with respective positions of resistance-related contributions
Relating to the vital MOSFET factor SiC-SiO2 interface, the next variations in comparison with silicon should be thought of:
- SiC has the next unit space atomic floor density in comparison with Si, resulting in increased densities of dangling Si and C bonds; defects within the gate oxide layer close to the interface might seem within the vitality hole and act as traps for electrons.
- The thickness of thermally grown oxide relies upon largely on the crystal face, in contrast to Si gadgets.
- SiC gadgets, working at increased drain-induced electrical fields within the blocking mode in comparison with Si gadgets (MV as a substitute of kV), require measures to restrict the electrical area within the gate oxide to take care of the reliability of the oxide in the course of the blocking section. Discuss with Determine 3 for TMOS, the place the vital level is the ditch angle, and for DMOS, the important thing level is the middle of the unit.
Because of the smaller barrier peak, the SiC MOS construction displays increased Fowler-Nordheim present injection below a given electrical area within the on-state in comparison with Si gadgets. Thus, the sector on the SiC facet of the interface should be restricted.
Determine 3: Left: Typical construction of planar MOSFET (half-cell), displaying two delicate areas for oxide area stress. Proper: Typical construction of trench MOSFET (half-cell), with a give attention to oxide area stress on the trench nook.
Based mostly on these concerns, it’s evident that SiC planar MOSFET gadgets certainly have two delicate areas for oxide area stress, as depicted within the left a part of Determine 3. First, the stress within the reverse-mode area area is mentioned, adopted by the interface between the drift area and gate oxide nearness, and eventually, the overlap of careworn gate and supply areas within the on-state.
The excessive electrical fields within the on-state are thought of extra vital, as there are not any appropriate gadget design measures to cut back area stress within the on-state so long as on-resistance efficiency should be ensured. Infineon’s total aim is to mix the low R_DS(on) provided by SiC with operation in a widely known secure oxide area power regime. Therefore, the choice was made to desert DMOS know-how and give attention to trench-based gadgets from the outset. Shifting away from planar surfaces with excessive defect density in direction of different favorable crystal orientations allows low channel resistance at low oxide fields. These boundary circumstances are the baseline for high quality assurance strategies established within the silicon energy semiconductor area to ensure the anticipated FIT charges in industrial and automotive functions.
CoolSiC MOSFET unit design goals to restrict the electrical area within the gate oxide throughout each on-state and off-state circumstances (see Determine 4). Concurrently, it gives a gorgeous 1200V level-specific on-resistance that may be achieved in a secure and reproducible method even in mass manufacturing. The low on-resistance ensures that the drive voltage degree is just V_GS = 15V, mixed with a sufficiently excessive gate-source threshold voltage (sometimes 4.5V), making it a benchmark within the SiC transistor area. The design’s particular options embrace channel orientation right into a single crystal orientation via a self-aligned course of. This ensures excessive channel mobility and a slender threshold voltage distribution. One other characteristic is the deep p trench intersecting with the precise MOS trench, permitting for efficient shielding of the decrease oxide nook.
Determine 4: Schematic illustration of the CoolSiC MOSFET unit construction
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