Design of Embedded Prolonged Communication Board Primarily based on Asynchronous Communication Unit Chip

“This design is developed based on the wants of the particular system. As a way to present as many features as attainable in a restricted house and make sure the reliability of the circuit, a extremely built-in asynchronous communication unit chip is used within the design, and the peripheral management circuit consists of programmable logic The system is carried out, and the interface is designed based on the PC/104 commonplace.

“

Authors: Xu Huigang, Bo Yuming

1 Introduction

PC/104 embedded management PC appeared within the late Eighties and shaped the IEEEP966.1 commonplace in 1992. On the one hand, it inherits all of the PC assets, and alternatively, it re-optimizes the design of the PC’s construction, quantity, energy consumption, reliability, and so on., making it totally suitable with IBM PC, and has the benefits of small measurement and low energy consumption. , Huge working temperature and excessive reliability. PC/104 embedded management PC adopts distinctive “self-stack” bus connection, modular construction, versatile and handy to make use of. The article-oriented {hardware} design technique it adopts makes the enlargement modules developed on the PC/104 commonplace have stronger versatility and longer lifespan. Due to its many benefits, PC/104 is more and more utilized in varied embedded methods, particularly in locations with excessive reliability necessities and harsh working environments, akin to navy command methods, weapons functions in management methods or industrial management methods. In these methods, it's usually not the management of a single laptop, however a number of computer systems kind a communication community to finish the management perform collectively. Due to this fact, for every embedded laptop, along with connecting the required peripherals, it's also obligatory to contemplate the communication between computer systems. Probably the most generally used communication technique between computer systems is realized through the use of serial port, so when designing these management methods, we frequently face the issue of scarcity of serial port assets.

Just like the desktop PC, the PC/104 embedded management PC typically offers two RS-232 serial ports, and the generally used serial communications embody RS-232 and RS-485. RS-232 is principally used for point-to-point communication, particularly for long-distance communication between two factors by means of MODEM; RS-485 is principally used for multi-computer communication, utilizing balanced differential circuit two-wire transmission, bus connection, and the gap is 1km The utmost price is 100kbps when inside, permitting 32 parallel drivers and 32 receivers to work in half-duplex mode. The 2 serial port assets offered by the PC/104 are usually not sufficient in lots of circumstances, as a result of the quantity and varieties of peripherals utilizing the serial port are rising, and the features of the serial port are additionally increasing. For instance, some PC/104 The gadgets linked to the serial port can be utilized because the system console, and so they all occupy worthwhile serial port assets; as well as, with the rise of communication necessities between computer systems, in multi-computer communication or a number of communication strategies are required. Within the system, the serial port assets are usually not sufficient. As well as, in some PC/104, the addresses of the 2 serial ports can't be modified, which brings inconvenience to make use of; PC/104 additionally doesn't present RS-442 or RS-485 serial ports, and the RS-485 bus is used when obligatory. When realizing multi-machine communication, it should be geared up with a converter from RS-232 to RS-485. For these difficulties, one of the best resolution is to develop embedded enlargement communication boards based on the PC/104 commonplace.

This design is developed based on the wants of the particular system. As a way to present as many features as attainable in a restricted house and make sure the reliability of the circuit, a extremely built-in asynchronous communication unit chip is used within the design, and the peripheral management circuit consists of programmable logic The system is carried out, and the interface is designed based on the PC/104 commonplace. Two RS-232 serial ports and two RS-485 serial ports are offered on the board, and the serial port handle and interrupt request quantity may be chosen by the person. The generality of the enlargement communication board can also be thought of within the design. The designed communication board conforms to the PC/104 commonplace and helps the plug-and-play perform. The person can set the serial port handle and interrupt request quantity based on the system useful resource circumstances and precise wants. Due to this fact, This design can be utilized as a reference for creating PC/104 commonplace embedded serial communication board. As well as, there's a distinctive construction within the {hardware} circuit of the RS-485 serial port on this design, which might notice the automated setting and conversion of the sign polarity together with the communication protocol.

2 Design technique of communication board

2.1 General construction

The general precept of this design is proven in Determine 1. The PC/104 bus within the determine is an ISA bus suitable with PC/AT. The design makes use of 8-bit information alerts D 0~D7, that are linked to the asynchronous communication unit by means of the info buffer circuit; 10 handle traces A0~A9, learn and write management Indicators IOR, IOW, handle allow sign AEN and reset sign RESET, these alerts, along with the handle choice circuit and the logic circuit designed within the PLD circuit, full the handle choice and varied logic management of the serial port, and management the inner registers of every serial port. The operation is set by the choice of the decrease three bits A 0, A1, and A2 of the handle; the interrupt quantity choice circuit mixed with the inner logic of the PLD circuit offers eight interrupt request numbers of IRQ3, 4, 5, 7, 9, 10, 11, 15 for select.

The asynchronous communication unit makes use of TI’s TL16C554, which incorporates 4 asynchronous transceiver models, every of which is suitable with the 16550, plus a degree conversion circuit to kind a serial port.

The RS-232 degree conversion circuit adopts MAX213, which offers five-way 232-to-TTL degree conversion and four-way TTL-to-232 degree conversion. One piece of MAX213 can notice the entire RS-232 interface perform.

The RS-485 degree conversion circuit adopts SN75176, which offers the conversion between 485 commonplace degree and TTL degree, and the receiving and sending elements may be managed individually.

The info buffer is undertaken by 74HC245, its transmission course is managed by the host IOR sign, and the chip choose sign is generated by the PLD.

The handle choice circuit offers the person to set the serial port handle, and the higher 4 bits A6-A9 of the handle are set to 0 or 1 by means of the short-circuit block to understand the handle setting.

2.2 Asynchronous communication unit

TL16C554 is a product of TI, with excessive integration and steady efficiency. It accommodates 4 independently operable programmable asynchronous transceiver models 16C550, which share information traces D7~D0, inside register handle traces A2~A0, learn Write sign traces IOR and IOW, DMA learn and write management TXRDY and RXRDY, reset RESET, clock XTL1 and XTL2. Every transceiver unit has its personal chip choose sign CS, interrupt request INT, information output TX, information enter RX and MODEM logic management alerts CTS, DCD, DSR, DTR, RI, RTS. Its inside practical modules are proven in Determine 2.

Every inside asynchronous transceiver unit is equal to a 16550, which is backward suitable with the 16450 and features a 16-byte first-in, first-out register, thereby lowering the variety of interrupts to the CPU. The programmable baud price may be as much as 1Mbps, the character construction of the interface may be chosen by the person, the addition and deletion of begin bits, cease bits and parity bits are mechanically accomplished, with programmable interrupt management and full MODEM management logical perform.

2.3 PLD circuit

Contemplating the scale limitation of the 104 commonplace, the design needs to be as compact as attainable. Due to this fact, the PLD circuit is used to generate the management alerts of the asynchronous communication unit and the info buffer circuit, and this circuit can also be used to understand the automated conversion of sign polarity when the 485 is linked. The PLD circuit adopts the EPM7064 of ALTERA Firm, which accommodates 4 logic array blocks, 64 macro cells, and 1250 logic gates accessible to be used. The event instrument makes use of MAX+PLUS II.

The PLD circuit primarily completes the next features:

(1) Choice of every asynchronous transceiver unit. The chip choice sign is generated by the logical relationship between the eight handle alerts A9~A3 and the learn and write management alerts IOR and IOW, wherein the A9~A6 bit handle alerts are despatched to a 4-bit comparator along with the sign of the handle choice circuit. For handle comparability, the handle choice circuit may be set by the person. On this method, the handle of the corresponding bit is modified by altering the short-circuit block within the handle choice circuit, thereby rising the person’s selection of handle and adaptability of use.

(2) Chip choose for bidirectional information buffer. Generated utilizing A9-A6 and read-write management alerts.

(3) 485 sign polarity choice. The 485 is linked by bus and transmitted in differential mode. The optimistic and detrimental polarities of the alerts between the 2 connecting traces are completely different. When utilizing, the terminals of the identical polarity should be linked.

When the nodes are far-off or the person doesn't know the polarity relationship of the sign traces, the right wiring can't be assured, and the wiring and debugging must be modified many occasions. Due to this fact, we've designed an automated polarity conversion circuit to facilitate the usage of embedded methods. The essential concept is that this, set an Electronic swap, and the host will ship a hard and fast check sign throughout communication initialization. If the slave finds that the acquired sign is incorrect, it can mechanically swap the course of the digital swap. If the acquired check sign is right, will probably be Preserve the unique connection. The digital swap acts as an XOR gate, which might invert or maintain the transmitted and acquired alerts, that's, when one sign on the enter is about to 1, the opposite enter sign may be inverted on the output, and when it's set to 0 The output sign stays unchanged. The management of the digital swap is realized by the D flip-flop. Through the initialization, the slave selects the D flip-flop based on the correctness of the acquired sign to generate an acceptable management degree to understand the management of the digital swap. Its logic precept is proven in Determine 3.

2.4 RS-485 interface circuit

When the pc communicates utilizing the RS-485 bus, when the system is linked, it's obligatory so as to add matching resistors to the RS-485 interfaces of the 2 computer systems on the farthest finish of the topology construction to eradicate the reflection of the sign, and it's also obligatory so as to add a hard and fast sign to the sign transmission line. bias voltage to extend the anti-interference skill. As a way to enhance the flexibility of the circuit and facilitate the usage of embedded methods, the design of the RS-485 interface circuit is proven in Determine 4. Within the determine, R 1=120Ω, R2=R3=560Ω, and the RS-485 interface circuit of the pc of various nodes may be set based on the wants of the bus connection.