Detailed explanation of the basic principles of Σ-Δ ADC topology
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# Detailed explanation of the basic principles of Σ-Δ ADC topology

Posted Date: 2024-02-02

It usually consists of two modules: a Σ-Δ modulator and a digital signal processing module, which is usually a digital filter. A brief block diagram and main concepts of a Σ-Δ ADC are shown in Figure 1.

Figure 1. Key concepts of Σ-Δ ADCs

The Σ-Δ modulator is an oversampling architecture, so we start our discussion with Nyquist sampling theory and scheme and oversampling ADC operation.

Figure 2 compares the ADC’s ​​Nyquist operation, oversampling scheme, and Σ-Δ modulation (also oversampling) scheme.

Figure 2. Nyquist comparison

Figure 2a shows the quantization noise when the ADC is operated in standard Nyquist mode. In this case, the quantization noise is determined by the LSB size of the ADC. F S is the sampling rate of ADC, F S /2 is the Nyquist frequency. Figure 2b shows the same converter, but now it is operating in an oversampling mode, sampling at a faster rate. The sampling rate is increased by K times, and the quantization noise is expanded to K × F S /2 bandwidth. A low-pass digital filter (usually with decimation) removes quantization noise outside the blue area.

Figure 2a. Nyquist scheme. The sampling rate is F S the Nyquist bandwidth is F S /2

Figure 2b. Oversampling scheme. The sampling rate is K × F S

The Σ-Δ modulator has one more feature, which is noise shaping, as shown in Figure 2c. The quantization noise of the analog-to-digital conversion is modulated and shaped, moving from low frequencies to higher frequencies (usually), and a low-pass digital filter removes it from the conversion result. The noise floor of a Σ-Δ ADC is determined by thermal noise and is not limited by quantization noise.

Figure 2c. Σ-Δ ADC scheme. Oversampling and noise shaping, sampling rate F MOD = K × F ODR

Sampling, modulation, filtering

Σ-Δ ADCs use an internal or external sampling clock. The ADC's master clock (MCLK) is often divided down before being used by the modulator; you should pay attention to this when reading the ADC data sheet, and understand the modulator frequency. The clock sent to the modulator sets the sampling frequency F MOD . The modulator outputs data at this rate to a digital filter, which in turn provides the data at the output data rate (ODR). Figure 3 shows this process.

Figure 3. Σ-Δ ADC flow: sampling from modulator output to digital filtered output

An in-depth look at first-order Σ-Δ modulators

A sigma-delta modulator is a negative feedback system, similar to a closed-loop amplifier. The loop contains the low-resolution ADC and DAC, as well as a loop filter. The output and feedback are roughly quantized, often with only one bit representing a high or low level of the output. The analog system of the ADC implements this basic structure, and the quantizer is the module that completes sampling. If conditions exist that guarantee the stability of the loop, then the output is a rough representation of the input. A digital filter takes this coarse output and reconstructs an accurate digital conversion of the analog input.

Figure 4 shows the 1 density output in response to a sine wave input. The rate at which the modulator output changes from low to high depends on the rate of change of the input. When the sine wave input is at positive full scale, the modulator output switching rate will decrease and the output will be mainly in the +1 state.Likewise, when the sine wave input is negative full scale, +1 and

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