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DFSPI IP Core from DCD helps all serial recollections obtainable in the marketplace.

DFSPI IP Core from DCD helps all serial recollections obtainable in the marketplace.

Posted Date: 2023-06-17

Digital Core Design, the main IP Core supplier and System-on-Chip design home, presents its newest DFSPI IP Core for entry to NOR and NAND Flash Gadgets. And if common NOR & NAND Flash IP is just not sufficient… DCD’s DFSPI IP Core helps additionally MRAM, pSRAM, DRAM, and EEPROM – combining the convenience of use with the reliability, low energy, and velocity below all situations, together with automotive, industrial, and different purposes.

Bytom, Poland June the sixteenth, 2023. DFSPI IP Core is an actual “combo” between all SPI IP Cores obtainable in the marketplace – it’s an SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL, QUAD, OCTAL SPI Bus Controller with DDR / DTR assist and non-compulsory AES Encryption) + NOR & NAND Flash Reminiscence Assist for all serial recollections obtainable in the marketplace. 

– As an possibility, the DFSPI controller has a built-in assist for HyperBusTM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification – explains Jacek Hanke, DCD CEO The identical the SPI Controller permits straightforward communication with all obtainable SPI FLASH recollections.

The DFSP IP Core is suitable with the xSPI JESD251 commonplace, which could be accessed by an ordinary AXI4 slave interface. It affords backward compatibility with Octal SPI, QSPI, DSPI, and SPI interfaces. Moreover, it helps the JEDEC SFDP Commonplace. The IP is designed to permit customers to shortly entry reminiscence from the xSPI gadget in SPI mode. Alternatively, customers can subject a command to change to a special mode. Moreover, a DMA command can be utilized to repeat reminiscence from the xSPI gadget to some other location on the bus.

The DFSPI can robotically drive chosen by SSCR (Slave Choose Management Register) slave choose outputs (SS3O – SS0O), and deal with SPI slave gadget to alternate serially shifted knowledge. It helps two DMA modes: single switch and multi-transfer. These modes enable DFSPI to interface with higher-performance DMA models, which might interleave their transfers between CPU cycles or execute a number of byte transfers. DFSPI is absolutely customizable, delivering it within the actual configuration that meets customers’ necessities.

DCD SPI cores, are a part of our rising peripheral household that additionally contains protocols reminiscent of I3C and IR. These cores have been efficiently applied in Embedded Microprocessor Boards, Client and Skilled Audio/Video, Dwelling and Automotive Radio, Low-power Cellular Purposes, Communication Techniques, and Digital Multimeters.

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About Digital Core Design

DCD has been based in 1999 and for the reason that very starting is targeted on IP Core Improvements. Throughout these 25 years firm mastered greater than 90 completely different architectures, which have been utilized in additional than 750 000 000 digital gadgets across the globe. Amin them one can discover e.g. World’s Quickest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Absolutely Scalable 32-bit CPU, 100% secure cryptographic system and 32-bit plus 64-bit RISC-V CPUs. Extra info at