Domestic RK3568J FSPI-based ARM+FPGA communication solution sharing
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Domestic RK3568J FSPI-based ARM+FPGA communication solution sharing

Posted Date: 2024-01-30

In recent years, with the continuous advancement of China's new infrastructure and Made in China 2025 plan, it has become increasingly difficult for a single ARM processor to meet the functional requirements of industrial sites. Especially nowadays, energy and power, industrial control, smart medical and other industries often require ARM more. + FPGA architecture processor platform to implement specific functions such as multi-channel/high-speed AD acquisition, multi-channel network ports, multi-channel serial ports, multi-channel/high-speed parallel DI/DO, high-speed data parallel processing, etc. Therefore, ARM + FPGA architecture processor The platform is becoming more and more popular in the market.

The ARM + FPGA architecture can bring comprehensive comparative advantages in performance, cost, power consumption, etc. ARM and FPGA can each perform their own duties, each taking advantage of the unique advantages of the original architecture, or they can collaborate with each other to solve more complex problems.

Common communication methods of ARM + FPGA include PCIe, FSPI, I2C, SDIO, CSI, etc. Today we mainly introduce the ARM + FPGA communication method based on FSPI.

Introduction to FSPI bus characteristics

FSPI (Flexible Serial Peripheral Interface) is a high-speed, full-duplex, synchronous serial communication bus. There is an ESPI controller in the RK3568 processor, which can be used to connect FSPI devices. It has the following characteristics:

-Supports serial NOR FLASH, serial NAND FLASH

-Support SDR mode

-Supports first-line, second-line and fourth-line modes

Compared with PCIe, FSPI can better achieve the requirements of "small data - low latency" and "big data - high bandwidth". In addition, when communicating with FPGA, users often prefer to use the FSPI interface for the following reasons:

-High-speed communication can be achieved using low-cost FPGAs, while the cost of FPGAs with PCIe interfaces has increased exponentially.

-FPGAs with PCIe interfaces tend to consume more power, while low-cost FPGAs consume less power. Generally speaking, low-power devices will also last longer.

ARM + FPGA communication measured data sharing based on FSPI

Hardware solution one: Chuanglong Technology TL3568F-EVM evaluation board (RK3568J + Logos-2).

Actual measured data: write rate 20MB/s+, up to 24MB/s, bit error rate 0%; read rate 26MB/s+, up to 30MB/s, bit error rate 0%.

TL3568F-EVM Evaluation Board Introduction:

Chuanglong Technology TL3568F-EVM is a heterogeneous multi-core domestic industrial evaluation board designed based on Rockchip RK3568J/RK3568B2 quad-core ARM Cortex-A55 processor + Unisoc Logos-2 PG2L50H/PG2L100H FPGA. It consists of core board and evaluation board It consists of a base plate and an ARM Cortex-A55 processing unit with a main frequency of up to 1.8GHz/2.0GHz. All components such as core board ARM, FPGA, ROM, RAM, power supply, crystal oscillator, and connectors adopt domestic industrial-grade solutions, with a 100% localization rate. At the same time, most components of the evaluation backplane also adopt domestic industrial-grade solutions.

Hardware solution two: Chuanglong Technology TL3568-EVM evaluation board (RK3568) + TLA7-EVM evaluation board (Artix-7)

Actual measured data: write rate 52.563MB/s, read rate 67.387MB/s, high bit error rate.

Note: Since this test is limited to the flying line connection method, the bit error rate measured at the 150MHz communication clock frequency is too high, and the test results are for reference only.

Detailed explanation of ARM + FPGA communication case based on FSPI

The following mainly introduces the FSPI communication case based on Rockchip RK3568J (hardware platform: Chuanglong Technology TL3568-EVM evaluation board) and Xilinx Artix-7 (hardware platform: Chuanglong Technology TLA7-EVM evaluation board). According to the instructions provided by Chuanglong Technology Use the case user manual to perform the operation to obtain the test results.

At the same time, tests were conducted based on Linux and Linux-RT systems, and test data of "small data - low latency" and "big data - high bandwidth" were obtained.

spi_rw case

(1) Case description

Case function: The ARM side runs the Linux system and performs read and write tests on the FPGA BRAM based on the FSPI bus.

The ARM side implements the SPI Master function. The principle is explained as follows:

a) Open the SPI device node, such as: /dev/spidev4.0.

b) Use ioctl to configure the FSPI bus, such as FSPI bus polarity and phase, communication rate, data length, etc.

c) Select the mode as single-wire mode, dual-wire mode or four-wire mode. When setting the FSPI bus to dual-wire mode, sending data is in single-wire mode, and receiving data is in dual-wire mode; when setting the FSPI bus to four-wire mode, sending data is in four-wire mode, and receiving data is in four-wire mode.

d) Send data to and read data from the FSPI bus.

e) Verify the data, and then print the read and write rate and bit error rate.

The FPGA side implements the SPI Slave function. The principle is explained as follows:

a) FPGA saves the data sent by SPI Master to BRAM.

b) When the SPI Master initiates reading data, the FPGA reads the data from the BRAM and transmits it to the SPI Master through the FSPI bus.

Figure 2 ARM end program flow chart

(2) Test results

ARM writes 4Byte random data to the FPGA BRAM through the FSPI bus (four-wire mode), then reads the data, performs data verification, and prints the FSPI bus read and write rate and bit error rate.

Finally, this test set the FSPI bus communication clock frequency to 24MHz, and the theoretical communication rate of the four-wire mode is: (24000000 / 1024 / 1024 / 8 x 4)MB/s ≈ 11.44MB/s. As can be seen from the figure below, this The actual measured write rate was 0.048MB/s, the read rate was 0.182MB/s, and the bit error rate was 0%.

image 3

Note: The hardware in the above case is connected using flying wires. The FSPI bus communication clock frequency needs to be set to a lower 24MHz, and a smaller test data amount needs to be set (which will result in a lower measured rate), otherwise bit errors will occur. . If the Chuanglong Technology TL3568F-EVM evaluation board (RK3568J + Logos-2) hardware platform is used for testing, the error-free communication rate will be greatly improved.

If the FSPI bus communication clock frequency is set to 150MHz, ARM writes 1MByte random data to the FPGA BRAM through the FSPI bus, then reads the data, loops 100 times without data verification, and finally prints the FSPI bus read and write rate and bit error rate.

Finally, this test set the FSPI bus communication clock frequency to 150MHz, and the theoretical communication rate of FSPI four-wire mode is: (150000000 / 1024 / 1024 / 8 x 4) MB/s ≈ 71.53MB/s. As can be seen from the figure below, the actual measured write rate was 52.563MB/s and the read rate was 67.387MB/s, which is relatively close to the theoretical communication rate.

Figure 4

Note: Since this test is limited by the flying line connection method, the bit error rate measured at the 150MHz communication clock frequency is too high, and the test results are for reference only.

rt_spi_rw case

(1) Case description

Case function: The ARM side runs the Linux-RT system and performs read and write tests on the FPGA BRAM based on the FSPI bus.

The ARM side implements the SPI Master function. The principle is explained as follows:

a) Open the SPI device node, such as: /dev/spidev4.0.

b) Use ioctl to configure the FSPI bus, such as FSPI bus polarity and phase, communication rate, data length, etc.

c) Select the mode as single-wire mode, dual-wire mode or four-wire mode. When setting the FSPI bus to dual-wire mode, sending data is in single-wire mode, and receiving data is in dual-wire mode; when setting the FSPI bus to four-wire mode, sending data is in four-wire mode, and receiving data is in four-wire mode.

d) Send data to and read data from the FSPI bus.

e) Verify the data, and then print the read and write rate and bit error rate.

The FPGA side implements the SPI Slave function. The principle is explained as follows:

a) Save the data sent by SPI Master to BRAM.

When the SPI Master initiates reading data, the FPGA reads the data from the BRAM and transmits it to the SPI Master through the FSPI bus.

Figure 5 ARM end program flow chart

(2) Test results

ARM writes 4Byte random data to the FPGA BRAM through the FSPI bus, then reads the data, performs data verification, and prints the FSPI bus read and write rate and bit error rate. Finally, this test set the FSPI bus communication clock frequency to 24MHz, and the theoretical communication rate of the SPI four-wire mode is: (24000000 / 1024 / 1024 / 8 x 4)MB/s ≈ 11.44MB/s.

As can be seen from the figure below, the actual measured writing rate this time is 0.179MB/s, the maximum time consuming for sending is 46us, the minimum time consuming is 20us, the average time consuming is 20us, the bit error rate is 0%; the reading rate is 0.187MB/s. The maximum transmission time is 46us, the minimum time is 19us, the average time is 40s, and the bit error rate is 0%.

Figure 6

Note: The hardware in the above case is connected using flying wires. The FSPI bus communication clock frequency needs to be set to a lower 24MHz, and a smaller test data amount needs to be set (which will result in a lower measured rate), otherwise bit errors will occur. . If the Chuanglong Technology TL3568F-EVM evaluation board (RK3568J + Logos-2) hardware platform is used for testing, the error-free communication rate will be greatly improved.

Review Editor Huang Yu


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