Five basic processes of wafer-level packaging
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Five basic processes of wafer-level packaging

Posted Date: 2024-01-25

In this article, we will focus on the other major method of semiconductor packaging - wafer level packaging (WLP). This article will discuss the five basic processes of wafer-level packaging, including: photolithography process, sputtering process, electroplating process, photoresist stripping process (PR Stripping) and metal etching ( Metal Etching) process.

Packaged complete wafer

Wafer-level packaging refers to the process before wafer cutting. Wafer-level packaging is divided into fan-in wafer-level chip packaging (Fan-In WLCSP) and fan-out wafer-level chip packaging (Fan-Out WLCSP). Its characteristic is that the wafer always remains intact during the entire packaging process. . In addition, redistribution layer (RDL) packaging, flip chip (Flip Chip) packaging and through silicon via (TSV) packaging are usually classified as wafer level packaging, although these packaging methods are only completed before wafer dicing. some processes. The metal and electroplating drawing patterns used in different packaging methods are also different. However, during the packaging process, these methods basically follow the following order.

After completing the wafer test, an insulating layer (Dielectric Layer) is made on the wafer as required. After the initial exposure, the insulating layer is exposed to the chip pad again through photolithography. Then, a metal layer is coated on the wafer surface through a sputtering process. This metal layer enhances adhesion to the electroplated metal layer formed in subsequent steps and also acts as a diffusion barrier to prevent chemical reactions within the metal. In addition, the metal layer also acts as an electron conduit during the electroplating process. Photoresist is then applied to form an electroplating layer, the pattern is drawn through a photolithography process, and then electroplating is used to form a thick metal layer. After electroplating is completed, the photoresist stripping process is performed, and the remaining thin metal layer is removed using an etching process. Finally, the electroplated metal layer creates the desired pattern on the wafer surface. These patterns can serve as leads for fan-in WLCSPs, pad redistribution in redistribution layer packages, and bumps in flip-chip packages. Each process will be introduced in detail below.

Photolithography process: drawing circuit patterns on a mask wafer

The English equivalent of photolithography is Photolithography, which is composed of "-litho (stone carving)" and "graphy (drawing)". It is a printing technology. In other words, photolithography is a circuit pattern drawing process. First, a layer of photosensitive polymer called "photoresist" is coated on the wafer, and then the wafer is selectively exposed through a mask engraved with the required pattern, and the exposed area is developed to Draw the desired pattern or shape. The steps of this process are shown in Figure 2.

In wafer-level packaging, the photolithography process is mainly used to draw patterns on the insulating layer, and then use the drawn pattern to create the plating layer, and to form the metal lines by etching the diffusion layer.

To understand the photolithography process more clearly, compare it to photography. As shown in Figure 3, photography uses sunlight as the light source to capture the subject, which can be an object, landmark, or person. Photolithography requires a specific light source to transfer the pattern on the mask to the exposure equipment. In addition, the film in the camera can also be compared to the photoresist coated on the wafer in the photolithography process. As shown in Figure 4, we can apply photoresist on the wafer through three methods, including spin coating (Spin Coating), film lamination (Film Lamination) and spray coating (Spray Coating). After applying the photoresist, soft baking is required to remove the solvent to ensure that the sticky photoresist remains on the wafer and maintains its original thickness.

As shown in Figure 5, spin coating applies the viscous photoresist to the center of the rotating wafer. The centrifugal force will cause the photoresist to spread toward the edge of the wafer, thereby dispersing it on the wafer with a uniform thickness. The higher the viscosity and the lower the rotation speed, the thicker the photoresist will be. On the contrary, the lower the viscosity and the higher the rotation speed, the thinner the photoresist will be. For wafer-level packaging, especially flip-chip packaging, the thickness of the photoresist layer must reach 30 μm to 100 μm to form solder bumps. However, it is difficult to achieve the desired thickness with a single spin coating. In some cases, it is necessary to repeatedly spin-coat the photoresist and perform multiple pre-bakes. Therefore, when a thicker photoresist layer is required, it is more effective to use the lamination method, because this method can bring the photoresist film to the required thickness from the initial stage without causing crystallization during processing. less waste and therefore more cost effective. However, if the surface of the wafer structure is rough, it will be difficult to attach the photoresist film to the wafer surface. In this case, using the lamination method will lead to product defects. Therefore, for wafers with very rough surfaces, spraying can be used to keep the photoresist thickness uniform.

After completing the photoresist coating and pre-baking, exposure is required next. Through illumination, the pattern on the mask is projected onto the photoresist on the surface of the wafer. Since positive photoresist (Positive PR) will soften after exposure, when using positive photoresist, it is necessary to open holes in the mask removal area. Negative photoresist (Negative PR) will harden after exposure, so holes need to be opened in the mask reserved area. Wafer-level packaging usually uses a mask aligner or a stepper as the photolithography process equipment.

Development is a process that uses a developer to dissolve the photoresist softened by the photolithography process. As shown in Figure 6, development methods can be divided into three types, including: puddle development (Puddle Development), which pours the developer into the center of the wafer and rotates it at low speed; immersion development (Tank Development), which The wafer is immersed in the developer at the same time; in spray development, the developer is sprayed onto the wafer. Figure 7 shows how the static development method works. After static development is completed, the photoresist is formed into the required circuit pattern through photolithography technology.

Sputtering process: forming a thin film on the wafer surface

Sputtering is a physical vapor deposition (PVD) process that forms a thin metal film on the surface of a wafer. If the metal film formed on the wafer is lower than the bumps in the flip-chip package, it is called Under Bump Metallurgy (UBM). Usually the under-bump metal layer consists of two or three layers of metal films, including: an adhesion layer that enhances wafer adhesion; a current-carrying layer that can provide electrons during the electroplating process; and solder wettability (Wettability), And it can prevent the formation of a diffusion barrier layer of compounds between the plating layer and the metal. For example, if the film is composed of titanium, copper and nickel, the titanium layer serves as the adhesion layer, the copper layer serves as the current-carrying layer, and the nickel layer serves as the barrier layer. Therefore, UBM is very important to ensure the quality and reliability of flip-chip packaging. In packaging processes such as RDL and WLCSP, the main role of the metal layer is to form metal leads, so it is usually composed of an adhesion layer and a current-carrying layer that can improve viscosity.

As shown in Figure 8, in the sputtering process, argon gas is first converted into plasma (Plasma), and then the ion beam is used to hit the target. The composition of the target is the same as the metal composition on which positive argon ions are deposited. After impact, the metal particles on the target will fall off and deposit on the wafer surface. By sputtering, the deposited metal particles have consistent directionality. Although the flat areas of the wafer are deposited to a uniform thickness, trenches or vertical interconnect vias (vias) may be deposited with varying thicknesses, so that such irregularities can result in deposited thickness parallel to the direction of metal deposition. The deposition thickness on the substrate surface is thinner than the deposition thickness on the substrate surface perpendicular to the metal deposition direction.

Electroplating process: forming the metal layer for bonding

Electroplating is a process in which metal ions in an electrolyte solution are reduced to metal and deposited on the wafer surface. This process requires externally provided electrons for a reduction reaction. In wafer-level packaging, an electroplating process is used to form thick metal layers. Thick metal layers can serve as metal leads for electrical connections, or as bumps for soldering. As shown in Figure 9, the metal on the anode is oxidized into ions and releases electrons to the external circuit. Metal ions oxidized at the anode and present in the solution can receive electrons and become metals after a reduction reaction. In the electroplating process of wafer-level packaging, the cathode is the wafer. The anode is made of the metal used as the electroplating layer, but insoluble electrodes such as platinum can also be used. If the anode plate is made of metal as a coating, the metal ions will dissolve from the anode plate and continue to diffuse to maintain a consistent ion concentration in the solution. If an insoluble electrode is used, the metal ions consumed by deposition onto the wafer surface must be replenished regularly to maintain the metal ion concentration. Figure 10 shows the electrochemical reactions occurring at the cathode and anode respectively.

When placing wafer plating equipment, it is usually necessary to ensure that the side of the wafer to be plated is facing down and the anode is placed in the electrolyte solution. Plating occurs when an electrolyte solution flows toward the wafer and collides forcefully with the wafer surface. At this time, the circuit pattern formed by the photoresist comes into contact with the electrolyte solution on the wafer to be plated. The electrons are distributed across the plating equipment at the edge of the wafer, and eventually the metal ions in the electrolyte solution meet the pattern drawn by the photoresist on the wafer. The electrons then combine with metal ions in the electrolyte solution and undergo a reduction reaction where the photoresist is patterned, forming metal leads or bumps.

Photoresist removal process and metal etching process: photoresist removal

After all process steps using photoresist patterns are completed, the photoresist must be removed through a photoresist stripping process. The photoresist stripping process is a wet process that uses a chemical solution called a stripper and is implemented through puddle, immersion, or spray methods. After forming metal leads or bumps through the electroplating process, the metal film formed by sputtering needs to be removed. This is a very necessary step because if the metal film is not removed, the entire wafer will be electrically connected causing a short circuit. Wet etching can be used to remove the metal film, and acidic etchant (Etchant) can be used to dissolve the metal. This process is similar to the photoresist stripping process, and as the circuit patterns on the wafer become more and more fine, the puddle method is also more widely used.

Fan-in wafer-level chip packaging process

In fan-in wafer-level chip packaging, qualified wafers will first enter the packaging production line. A metal film is prepared on the wafer surface through a sputtering process, and a thicker layer of photoresist is coated on the metal film. The thickness of the photoresist needs to exceed the metal leads used for packaging. The circuit pattern is drawn on the photoresist through the photolithography process, and then the copper electroplating process is used to form metal leads in the exposed area. Then the photoresist is removed, and the chemical etching process is used to remove the excess thin metal film. Then an insulating layer (Dielectric Layer) is prepared on the surface of the wafer, and the photolithography process is used to remove the solder ball placement area. of insulation layer. Therefore, the insulating layer is also called "Solder Resist", which is the passivation layer (Passivation Layer) in wafer-level chip packaging, that is, the final protective layer, used to distinguish the solder ball placement area. If there is no passivation layer, the solder balls attached to the metal layer will continue to melt and cannot maintain their spherical shape when processes such as reflow soldering are used.

After using the photolithography process to draw the circuit pattern on the insulating layer, the solder balls are attached to the insulating layer through the ball planting process. After the ball installation is completed, the packaging process also ends. After the entire packaged wafer is cut, multiple independent fan-in wafer-level chip packages can be obtained.

During the ball placement process, solder balls need to be attached to the wafer-level chip package. The key difference between traditional packaging processes and wafer-level packaging processes is that the former places solder balls on the substrate, while the latter places solder balls on top of the wafer. Therefore, except that the template used for flux coating and ball mounting needs to be consistent in size with the wafer, the flux coating, ball mounting process, and reflow soldering process all follow the same steps.

In addition, the reflow soldering equipment uses a reflow soldering method based on a heating plate, as shown in the figure, rather than a convection hot air reflow soldering method (Convection Reflow) involving a carrier. Wafer-level reflow equipment applies different temperatures to the wafer at different processing stages in order to maintain the temperature conditions required for the reflow operation and ensure that the packaging process can proceed smoothly.

Flip chip packaging bump process

Bumps in flip-chip packages are completed based on wafer-level processes, and subsequent processes are the same as traditional packaging processes.

To ensure that the bumps have sufficient height, a photoresist that can be applied thickly on the wafer needs to be used. Copper pillar bumps (CPB) need to be formed through two processes of copper plating and solder plating. The solder used is usually a lead-free tin-silver alloy. After electroplating is completed, the photoresist is removed and a metal etching process is used to remove the sputtered under-bump metal layer (UBM). These bumps are then made into spherical shapes through wafer-level reflow equipment. The solder bump reflow process used here can minimize the height difference of each bump, reduce the roughness of the solder bump surface, and at the same time remove the oxides contained in the solder, thereby ensuring an increase in bonding during the flip bonding process. combined strength.

redistribution layer packaging process

The redistribution layer packaging process is used to form new pads on the original pads of the wafer to carry additional metal leads. This process is mainly used for chip stacking. Therefore, as shown in the figure, the encapsulation process after the reassignment layer process follows the traditional encapsulation process. During the chip stacking process, each individual chip needs to repeat the two processes of chip mounting and wire bonding.

In the redistribution layer process, a metal film is first created through a sputtering process, and then a thick layer of photoresist is applied to the metal film. The photolithography process is then used to draw the circuit pattern, and a gold layer is electroplated on the exposed area of ​​the circuit pattern to form metal leads. Since the redistribution process itself is a pad rebuilding process, it is important to ensure wire bond strength. This is why gold, a material widely used for wire bonding, is used for electroplating.

Fan-out wafer-level chip packaging process

In the fan-out wafer-level chip packaging process, a layer of film needs to be attached to a carrier equal to the shape of the wafer. After cutting the wafer, high-quality chips are attached to the film at a certain distance, and then the chip spacing area is molded to form a new shape. After the wafer molding is complete, the carrier and film are removed. On the newly formed wafer, wafer equipment is then used to create metal wires and attach solder balls for packaging. Finally, the wafer is cut into individual packages.

1. Wafer molding

Wafer molding is an important process when making fan-out wafer-level chip packages. For fan-out wafer-level chip packages, the wafer plastic film needs to first attach a wafer carrier of the same shape to the chip and then place it into the molding frame. Liquid, powdery or granular epoxy resin molding compound (EMC) is added to the molding frame, and is pressurized and heated to form the film. Wafer molding is not only an important process in the fan-out wafer-level chip packaging process, but also an indispensable process for producing known good stacked chips (KGSD) using the through silicon via (TSV) process.

Through silicon via packaging process

The figure below shows the through silicon via packaging process steps using the Via-middle method. Vias are first formed during the wafer fabrication process. Subsequently during the packaging process, solder bumps are formed on the front side of the wafer. The wafer is then attached to a wafer carrier and back-grinded. After bumps are formed on the back of the wafer, the wafer is cut into independent chip units and stacked.

Next, the basic process of through holes will be briefly summarized. First, in the front-end of Line process, transistors, such as complementary metal oxide semiconductors, are produced on the wafer. A hard mask (Hard Mask) 6 is then used to draw the circuit pattern in the through silicon via formation area. The dry etching process is then used to remove the areas not covered by the hard mask to form deep trenches. The chemical vapor deposition process (Chemical Vapor Deposition) is then used to prepare insulating films, such as oxides. This layer of insulating film will be used to isolate copper and other metal substances filled in the groove to prevent the silicon wafer from being contaminated by metal substances. In addition, a thin metal layer will be prepared on the insulating layer as a barrier.

This thin layer of metal will be used to electroplat the copper layer. After electroplating is completed, chemical mechanical polishing (Chemical Mechanical Polishing) technology is used to keep the wafer surface smooth, and at the same time remove the copper substrate on the surface to ensure that the copper substrate only remains in the grooves. Then the wafer manufacturing is completed through the back-end of Line process.

When manufacturing chip stack packages using through silicon via technology, there are generally two types of packaging methods that can be used. The first method is substrate packaging utilizing 3D chip stacking technology. The second method requires creating KGSD, and then making 2.5D or 3D packaging based on KGSD. The following will introduce in detail how to create KGSD and the process of making 2.5D packaging based on KGSD.

As a chip stack package made using through-silicon via technology, the production of KGSD requires additional packaging processes, such as 2.5D packaging, 3D packaging, and fan-out wafer-level chip packaging. High-bandwidth memory (HBM) is a KGSD product. A typical example. Since KGSD needs to undergo additional packaging processes, its solder bumps used as connection pins need to be finer than traditional solder balls. Therefore, the chips in the 3D package are stacked on the substrate, while the chips in the KGSD are stacked on top of the wafer. The wafer can also be regarded as the bottom chip of the KGSD. In the case of HBM, the chip at the bottom is called the base chip or base wafer, while the chip above it is called the core chip.

The process of this method is as follows: First, bumps are made on the front side of the base wafer and the core wafer through the flip process. When making a 2.5D package, the base wafer needs to have bumps arranged so that it can be attached to the interposer; conversely, the bump layout on the core wafer facilitates chip stacking on the front side of the wafer. After the bumps are formed on the front side of the wafer, the wafer should be thinned and bumps also need to be formed on the back side of the wafer. However, as mentioned earlier when introducing the back grinding process, care must be taken to cause wafer bending during the thinning process. In the traditional packaging process, the wafer can be attached to the patch ring frame before thinning to prevent the wafer from bending, but in the through-silicon via packaging process, since the bumps are formed on the back of the wafer, this This protection method is not applicable. To solve this problem, the Wafer Support System came into being. Using the wafer carrier system, the front side of the wafer with bumps can be attached to the wafer carrier with the help of temporary adhesive, while the back side of the wafer is thinned. At this time, the wafer is attached to the wafer carrier and will not bend even after thinning.

In addition, because the wafer carrier is in the same form as the wafer, it can also be processed using wafer equipment. Based on this principle, bumps can be made on the back of the core wafer. When the bumps on the front and back of the core wafer are completed, the carrier can be debonded. The wafer is then attached to the patch ring frame and cut according to the traditional packaging process. The base wafer is always attached to the wafer carrier, and the chips cut from the core wafer are stacked on the base wafer. After the chip stacking is completed, the base wafer is molded, and then the wafer carrier is debonded. At this point, the base wafer becomes a molded wafer on which the core wafer is stacked. The wafer is then ground to the thickness required to make 2.5D packages, and then cut into individual chip units to make KGSD. After HBM finished products are packaged, they will be shipped to customers who make 2.5D packages.

Wafer carrying system process

The wafer carrying system refers to the system for further processing of the backside thinning of the wafer. This process is generally used before backside grinding. The wafer carrying system process involves two steps: the first is carrier bonding, which requires attaching the wafer used for through-silicon via packaging to the carrier; the second is carrier debonding, that is, bumping on the back of the wafer, such as After the production and other processes are completed, the slides are separated.

The figure below shows the process steps of the wafer carrier system. First, a temporary adhesive is applied to the surface of the wafer to attach it to the carrier; after the processing on the back of the wafer is completed, the carrier can be debonded and the residual adhesive removed to ensure that the wafer Surface clean.

When performing carrier bonding, you need to pay attention to several factors: first, the overall thickness of the wafer after carrier bonding should be uniform; second, there should be no gaps on the bonding surface, and the alignment of the two wafers should be accurate; in addition, The edges of the wafer should be protected from adhesive contamination and bending of the wafer should be avoided during handling. During the debonding process of the carrier, attention should also be paid to: avoid damage after the wafer is detached from the carrier, such as edge peeling (chipping)7 or cracks, etc.; avoid adhesive residue; avoid bump deformation.

In the packaging process based on the wafer carrier system, the debonding of the carrier is a relatively complex and important process. Therefore, the industry has proposed and developed a variety of debonding methods, and developed corresponding temporary adhesives for each debonding method. Typical debonding methods include thermal technology, peeling after laser ablation, chemical dissolution, chemical cleaning after machine peeling, etc.

Wafer edge rib cutting process

As shown in the red circle in the upper half of Figure 8, the wafer packaged using the through-silicon via process is bonded to the wafer carrier. After back grinding, its edges will become sharper. In this state, the wafer will subsequently undergo processes such as photolithography, metal film preparation, and electroplating to create bumps on the back. These processes will increase the risk of wafer edge peeling. Edge cracks may extend into the interior of the wafer, making subsequent processes impossible and eventually causing serious loss of quality products. To avoid this problem, for wafers packaged using the through-silicon via process, the front edge of the wafer should be ribbed and the trimmed portion should be removed before chip bonding. As shown in the lower half of the figure, when the ribbed wafer is attached to a wafer carrier and back-grinded, the sharp, raised edges disappear. Therefore, the risk of wafer edge peeling in subsequent processes is also eliminated. During the rib cutting process, the rotating wafer cutting blade passes through the edge of the wafer and cuts off the designated edge area.

stacking process

In the through silicon via packaging process, the bumps formed on the front and back sides of the wafer are used for bonding to facilitate stacking. Similarly, during rewind bonding, the mass reflow process 8 and the thermocompression process are also used for bonding. According to different stacking methods, the stacking process can be divided into chip-to-Chip stacking, chip-to-Wafer stacking, and wafer-to-Wafer stacking.

When stacking chips using the through-silicon via process, micro-bumps are used. Therefore, the spacing between bumps is very small, and the spacing between stacked chips is also very small, which is why the thermal compression process, known for its reliability, is widely used. However, the thermal compression process also has disadvantages, that is, it is time-consuming and has low productivity, because it will inevitably take time to heat and pressurize during the bonding process. Therefore, the trend of thermal compression process being gradually replaced by batch reflow soldering process is becoming increasingly obvious.

Source: Semiconductor Industry Watch

Review Editor: Tang Zihong


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