GaN-based high-efficiency 1.6kW CrM totem pole PFC reference design TIDA-00961 FAQ

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GaN-based high-efficiency 1.6kW CrM totem pole PFC reference design TIDA-00961 FAQ

Posted Date: 2024-01-11

Author: Aki Li, Rayna Wang

High-frequency critical mode (CrM) totem pole power factor correction (PFC) is an easy way to design high-density power solutions using GaN. TIDA-00961 reference design uses TI’s 600V GaN power stage LMG3410 and TI’s Piccolo™

High-frequency critical mode (CrM) totem pole power factor correction (PFC) is an easy way to design high-density power solutions using GaN. The TIDA-00961 reference design uses TI's 600V GaN power stage LMG3410 and TI's Piccolo™ F280049 controller. The power stage size is 65 x 40 x 40mm, the power density is greater than 250W/inch3; the efficiency can reach 98.7% under 230V AC input and full load; the power factor is >0.99, and the input current THD is small. This design is suitable for a variety of space-constrained applications such as servers, telecommunications, and industrial power supplies. At the same time, the hardware design meets conducted emission, surge and EFT requirements, helping engineers achieve 80+ Titanium specifications.

TIDA-00961 provides a set of cutting-edge solutions for the industry. This FAQ is designed to solve common problems encountered by a large number of engineers in the process of learning this reference design.

1. How to obtain the control program of TIDA-00961?

All materials of TIDA-00961 (including schematics and programs) are open and can be obtained in DigitalPower SDK. Program file location:


DigitalPower SDK can be downloaded and installed from the official website, which also contains reference routines for all chips, the latest reference design source code, powerSUITE design tools, etc. (download link)

2. The design power of the reference solution is 1.6kW. If you want to apply it to higher power applications, any suggestions?

The full-load design power of TIDA-00961 is 1.6kW (high line 230V) and 1.2kW (low line 110V). This is mainly due to the design power of the GaN half-bridge power board, and because the peak current in CrM control mode is twice the average current. , so it is recommended that in CrM mode, the corresponding design power of a GaN half-bridge power board is 1kW. Therefore, this reference design can actually work at a full load power of 2kW (has passed actual testing). If you want to apply this solution to higher power situations, such as 3kW, you can refer to the following three implementation methods:

1) Use multi-tube parallel connection, for example, double-tube parallel connection to reduce the conduction loss introduced by GaN on the power loop to half of the original, thereby increasing power without changing the topology and control method;

2) Increase the number of phases in interleaved parallel connection. For example, upgrade the original two-phase interleaved parallel topology to a three-phase interleaved parallel topology. At the same time, in terms of control, change the phase shift angle of the other two phases from 1800 to 1200 and 2400.

3) The GaN used in the current solution is LMG3410 (Rdson=70mΩ). The next generation GaN Polaris is about to be launched (expected to be in the first half of 2019. You can currently contact the TI sales team to apply for samples), which has lower on-resistance (Rdson= 50mΩ), a single tube can bear greater power and is pin-compatible with the LMG3410. There is no need to change the hardware topology and software control. Therefore, directly using Polaris is the easiest way to increase system power.

3. The PFC reference design PMP20873, which also uses GaN to achieve high efficiency, is based on CCM mode. What are the reasons for using CrM control in the solution?

TI GaN LMG3410 avoids the reverse recovery problem of Si MOSFET, so it can be used to implement the CCM operating mode of the totem pole topology. You can see the reference design PMP26873, but note that the switching frequency of this design is 100kHz. If you want to improve it by further increasing the switching frequency Power density, CCM working mode will encounter bottlenecks. Although the switching loss performance of GaN has advantages compared to Si MOSFET, specifically (see Figure 1), its turn-on loss is higher than the turn-off loss during hard switching. Once the switching frequency is increased to several hundred or MHz, the proportion of switching losses will decrease. will be greatly improved. Therefore, achieving zero-voltage turn-on (ZVS) by using CrM mode provides the possibility for higher switching frequency and higher power density.

Figure 1 Turn-on loss and turn-off loss corresponding to GaN during hard switching

4. What is the reason why the reference design uses a two-phase interleaved topology?

1) By interleaving two phases in parallel, the power level of the system can be doubled.

2) Compared with two-phase staggered parallel connection, a single-phase circuit with the same power has a larger effective current value in CRM mode. Since the peak current during the switching cycle is twice the average current, the current fluctuation is large, which will inevitably increase the line and The conduction loss of the device. Through staggered parallel connection, the ripples of each phase input current or each phase output current cancel each other, which greatly improves the THD performance and reduces the size requirements for the input differential mode filter and output capacitor. At the same time, the reduction of ripple also makes the input filter losses on the converter and output capacitor are reduced.

5. How to understand Phase shedding?

Phase shedding is used to improve system efficiency. When the load becomes smaller (less than the set current threshold), phase shedding is enabled to turn off the second phase, thereby improving the efficiency of the system at light load. It is worth noting that the moment when Phase shedding is enabled needs to be controlled to occur at the moment when the voltage crosses zero, when the energy in the loop is minimal, thereby avoiding overshoot or oscillation of the current due to Phase shedding.

6. In the program, when the load becomes larger and the second phase is added, why is there a processing of gv_out = gv_out*(0.6)?

The coefficient of 0.6 is used to prevent potential voltage overshoot problems. Under light load conditions, only one phase operates. At this time, if the load increases to exceed the set threshold, the second phase needs to be enabled immediately. If the duty cycle adopted by the second phase is different from that of the first phase, The duty cycle was the same at the previous moment, which is equivalent to producing twice the energy output as before. Since the load only increases slightly at this time, it will cause a large output voltage overshoot. Therefore, theoretically the coefficient in the formula should be 0.5, but considering that the actual load is still increasing, it is more appropriate to use a coefficient of 0.6.

7. The PWM frequency of the reference design is up to 1.2MHz. What is the main guarantee?

3) The wide bandgap semiconductor device GaN makes MHz switching frequencies possible. TI's LMG3410 has a built-in driver, which minimizes the impact of loop parasitic inductance and can still maintain very low losses under high-frequency switching actions.

4) Achieving precise and efficient control of the system under such high-frequency switching relies on the excellent computing capabilities of TI's new generation C2000 MCU TMS320F28004x. With a main frequency of 100MHz, in addition to the floating point operation unit (FPU), a trigonometric function operation unit (TMU) is added. Through hardware acceleration, the speed of complex operations such as division, sine, cosine, and root mean square is greatly accelerated, thus ensuring that high Implementation of algorithms such as frequency interrupt inner loop control and ZVS control. At the same time, the Type 4 ePWM of F28004x can achieve high-precision control of duty cycle, period, and dead time, maintaining control precision and accuracy under high-frequency switching.

8. How to ensure consistency and error-free control of two-phase interleaving under high-frequency operation?

This reference design uses the new generation of C2000 MCU TMS320F28004x. The latest Type 4 ePWM introduces one-time loading and global loading functions, ensuring that duty cycle, phase and other registers are updated simultaneously based on the same set event, which can avoid potential problems in multi-phase control. Phase control errors in applications.

9. When the switching frequency reaches MHz, are there any challenges in terms of EMI?

Compared with traditional PFC applications in CCM mode, the switching frequency of this reference design can reach up to MHz, and it adopts two-phase interleaved parallel control. In theory, it can greatly reduce the size of the differential mode filter. However, it is also noted that the CrM mode is a variable frequency Control, the requirements for filter design will increase accordingly; on the other hand, GaN LMG3410 can flexibly adjust dv/dt by adjusting the size of the external resistor, which helps to improve EMI problems. Currently, the development board of this reference design is planned to be delivered for EMI testing, and we will update the test results as soon as possible.

10. The controlISR interrupt frequency in the program is 50kHz and contains a lot of calculations. How much time is left after the interrupt runs?

The controlISR interrupt is mainly used for current loop control, phase-locked loop calculation, etc. The running time required to obtain this interrupt through actual testing is 12.4µs, and the CPU bandwidth occupied is about 60%, see Figure 2. In addition, the control program also contains two other interrupts, namely: tenKHzISR with a frequency of 10kHz, used for voltage loop and phase shedding processing, with a required running time of 20.8 µs; pwmISR with a frequency of 1/3 of the PWM frequency, used for ZVS adjustment and phase shift synchronization control, the required run time is 2.04 µs. It can be seen that thanks to the excellent computing power of F28004x, the CPU bandwidth usage of this control system is relatively low, and it can still provide sufficient margin for additional user functions.

Figure 2 Time required for system interruption to run

11. There is no protection circuit such as OCP in the schematic diagram. How to implement this protection function?

1) This solution does not require an external OCP circuit. By sampling the input current, it directly uses the window comparator (CMPSS) on the F28004x chip to simultaneously realize the OCP of the positive and negative half cycles of the input current. It does not need to be judged and processed by the CPU, and it can be implemented in about 60ns through hardware. rapid protection capabilities.

2) In addition, TI GaN LMG3410 integrates OCP, OTP and other protection functions. If there is an overcurrent in the power loop, LMG3410 can immediately shut down to implement the protection function.

12. The boost inductance of the PFC in the schematic diagram is 15uH. How to avoid the current spike when the input voltage crosses zero?

The boost inductor in the solution is small, and even a small voltage will cause rapid current changes. Especially when the voltage crosses zero, current spikes are prone to occur. Therefore, this design uses soft-start control at the moment when the input voltage crosses the zero point. By judging the size of the input voltage and using a state machine to control the switching sequence of GaN and MOSFET, the current spike at the zero crossing point is eliminated and the THD of the current is further improved.For the specific principle of soft start, please refer to Section 2.4.4 in the TIDM-1007 reference design description.

13. How to determine the turn-on and turn-off time of the power tube within a switching cycle?

The control mode of this system is based on the constant on-time mode. The control system consists of an output voltage outer loop and an input current inner loop. The turn-on time Ton mainly depends on the voltage loop. At the same time, the current inner loop is introduced for fine-tuning to optimize the THD of the input current. The off-time Toff is calculated based on the volt-second balance principle.

14. Which hardware circuits are the effective parts of the ZVS detection circuit?

Answer: We have adopted a variety of ways to implement ZVS during the design process. The currently effective ZVS detection signals are ZVS1_2 and ZVS2_2. The circuits used to generate ZCD_OUTPUT1/2, ZVS1/2 and CROSSOVER signals are redundant and no longer used.

Figure 3 Redundant circuit

15. How is ZVS implemented in the reference design?

The reference design implements ZVS through two mechanisms: adjusting the dead time before turning on the main working tube and adjusting the conduction time of the freewheeling tube, as follows:

1) Adjust the dead time before turning on the main work pipe

Through circuit analysis, it can be found that when the freewheeling tube is turned off and before the main working tube is turned on, the Vds voltage on the main working tube satisfies:


When the input and output voltages meet Vin0.5Vout, Vds cannot reach 0 through resonance. To achieve the full range of ZVS, additional control algorithms need to be added. The specific idea is to provide a negative inductor current Io for a period of time (dead time) after the inductor current drops to 0 to inject energy into the resonant circuit so that Vds can reach 0.

When Vds drops to 0, there is

To further obtain the dead time,

In addition, when Vin

2) Adjust the conduction time of the freewheel tube tooff_calc

Through the external ZVS detection circuit, which is used to detect the slope of Vds (dv/dt), ZVS1_2 is generated as the input signal of the window comparator (CMPSS) on the F28004x chip. If a large ZVS1_2 is generated when the main working tube is turned on, it is judged by CMPSS that ZVS is not realized at this time (zvs_lost = 1), so the conduction time toff_calc of the freewheeling tube needs to be increased in the next switching cycle; if it is judged that ZVS is realized at this time ZVS, then reduces the conduction time of the freewheeling tube in the next switching cycle to avoid introducing too much negative current that affects the system efficiency. Therefore, this is a dynamic adjustment mechanism. In addition, when the program calculates toff_calc, for Vin>0.5Vout conditions, toff_calc also adds a delay time that is positively related to the input voltage based on the volt-second balance calculation result. For details, see the calculation of acSine_diff.

16. Is the dead time from when the main working tube is turned off to when the freewheeling tube is turned on fixed?

The dead time corresponds to the resonance time of the parasitic capacitance of the switch tube and the boost inductor. In traditional analog control, a fixed dead time setting is generally used, but within an input voltage AC cycle, the resonance time changes. Therefore, Too long or too short dead time is not conducive to improving efficiency, and can easily lead to oscillation problems caused by inappropriate switching action timing. This design uses adaptive dead zone control and uses dead time in each switching cycle to further improve system efficiency.

17. Can the system implement ZVS across the entire range?

Answer: In the currently updated program, the working conditions that can achieve full-range ZVS control are: the effective value of Vin is less than 210V.when

When the effective value of Vin is greater than 210V, there is currently no adjustment of the conduction time of the freewheeling tube (ZVS extension) based on ZVS detection. The current code is used for the V2 version hardware circuit. In the future, the code will be optimized so that the ZVS extension can work on the V3 version circuit. 210V or above.

18. How to understand SPLL_1PH_SOGI_FLL_run(&spll3,ac_vol_senseed) and what is the purpose of phase locked loop?

SPLL_1PH_SOGI_FLL_run, as one of the C2000 official library functions, can be further understood through DigitalPower SDK. For specific usage and principles, please refer to the document "Digital Power Library USER'S GUIDE". The file location is C:tic2000C2000Ware_DigitalPower_SDK_1_01_00_00docs.

In this program, the phase-locked loop performs frequency and phase detection on the input voltage in order to:

1) Determine the timing of switching between positive and negative half-cycle opening states;

2) Perform soft-start processing on the switching signal when the voltage crosses zero point, so that the current at the zero-crossing point transitions smoothly and avoids the generation of current glitches;

3) The sine value corresponding to the voltage phase is used to calculate the current given value of the current loop (ac_cur_ref_inst = ac_cur_ref*acSine, ac_cur_ref is the output of the voltage loop), which is used for accurate tracking of the current loop;

19. In the program, the statement gi_out=DCL_runPI_C1(&gi, SFRA_F_INJECT(ac_cur_ref_inst), ac_cur_sensed) that controls the current loop, how do you understand SFRA_F_INJECT(ac_cur_ref_inst)?

This control program integrates the Software Frequency Response Analyzer (SFRA) function. Engineers can directly use this program to enable the SFRA function to obtain the system's loop bandwidth and other parameters online without adding any hardware equipment. Once the SFRA function is enabled, the signal represented by SFRA_F_INJECT (ac_cur_ref_inst) is the small signal interference amount of a specific frequency superimposed on ac_cur_ref_inst. It is worth noting that the SFRA function is a tool that serves the project development stage. Once the system parameters are debugged, the corresponding SFRA embedded code can be removed to release the bandwidth it occupies. For details, see the specific usage instructions of SFRA.

20. Why does the test result given in the manual show that the THD value jumps when the system is working near Pout = 800W (Vin = 230V)?

Figure 4 THD test results

Since this phase will change from phase shedding to addition (2nd phase on), the load value of each phase after addition becomes half of the original single-phase operation. Since the THD at low load is worse than that at high load, the THD value will suddenly increase when the second phase is turned on.

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