High-efficiency design of high-voltage gallium nitride transistor gate driver optimization

Within the area of power electronics, there was a big enhance in demand for high-voltage (HV) gallium nitride (GaN) transistors lately. In comparison with conventional silicon-based units, high-voltage gallium nitride transistors supply important benefits, resembling decrease conduction and switching losses, increased energy density, and improved effectivity. These options help quite a few functions throughout renewable power methods, electrical autos, industrial motor drives, aerospace know-how, and extra.

In a digital tutorial on the 2023 PowerUp Expo, Eric Persson, Senior Chief Engineer at Infineon Applied sciences, identified that 600/650V GaN transistors are known as high-voltage GaN transistors. GaN has a number of benefits over comparable Rds(ON) silicon or silicon carbide MOSFETs:

1. No reverse restoration impact attributable to minority carriers, facilitating exhausting switching.
2. Decrease gate cost because of decrease enter capacitance and threshold voltage.
3. Low and linear output capacitance, decreasing switching losses even in soft-switching topologies.
4. No avalanche traits, making it extra sturdy towards high-voltage occasions like lightning transients.

Nevertheless, most gate driver circuits for GaN transistors sometimes use silicon-based chips, and this hybrid answer of silicon chip + GaN transistor introduces extra parasitic inductance points. The sources of those inductances may be wires or on-board traces, that are extra prevalent in high-frequency switching situations. Subsequently, to totally harness the potential of GaN transistors, it turns into essential to design gate drivers that guarantee dependable and high-performance operation. Nicely-designed gate drivers, in line with these utilized by Infineon for Energy Issue Correction (PFC) items, can mitigate numerous points like excessive switching losses, bigger structure dimension, retaining EMI inside limits, and working at decrease effectivity at increased frequencies. It additionally simplifies thermal administration and ensures a dependable and aggressive system value. This text explores one of many normal approaches to designing gate drivers and the important thing design methods utilized by Infineon to develop optimized gate drivers for high-voltage gallium nitride transistors.

Built-in Gate Drivers for Gallium Nitride Energy Units

To develop an built-in gate driver, a bunch of researchers applied enhancement (E)-mode GaN energy switches and GaN-based single-chip built-in gate drivers on a business 650V silicon-based GaN platform. This integration eliminates further processing steps and simplifies the manufacturing course of. The gate driver makes use of low-voltage E/D-mode HEMTs to type the gate driver circuit, attaining exact management by reshaping the transmission enter PWM sign.

To make sure dependable and environment friendly operation, a number of design elements have been thought of. The gate driver voltage was set at 6-7V to make sure full conduction of the ability swap. The gate cost required to activate the GaN energy transistor (roughly ~2 nC) is considerably decrease than that of silicon energy transistors, thereby enhancing effectivity.

In conventional designs, slower switching speeds have been noticed because of the charging strategy of the ability swap. To beat this limitation, a cost pump circuit was launched within the gate driver. This strategy ensures a continuing voltage (VGS) within the pull-up charging transistor, thereby enhancing the charging velocity and decreasing gate stress. The brand new Gen-II gate driver design presents increased driving functionality, rail-to-rail output, and environment friendly GaN energy system turn-on, as proven in Determine 1.

[Figure 1: Comparison of Gen-1 and Gen-2 GaN power device circuits (source: [1])]

The chip traits of the gate driver reveal its capability to effectively drive a 650V/130mΩ GaN energy transistor. The static present of the gate driver is roughly 6mA, minimizing static energy consumption. Propagation delay measurements point out quick turn-on and turn-off occasions of solely 2.9ns and 1.7ns, respectively, because of the lateral GaN energy system’s superior present density and smaller intrinsic capacitance.

Adverse Gate Bias to Forestall Overcharging of Gate-Supply Capacitance

Through the turn-on course of, resembling from 0V to 50V, a peak present is injected into the gate node inside a brief interval, which might trigger charging of the gate-source capacitance and pointless turn-on of the high-side transistor. Persson defined how making use of a unfavourable bias to the gate as a substitute of zero voltage prevents charging of the gate-source capacitance, making certain that the high-side transistor stays within the off state. For 650V high-voltage gallium nitride transistors, a unfavourable bias of roughly -2.5V to -3V is adequate to attain the specified consequence and forestall overcharging.

A easy DC-DC converter can be utilized to implement this gate driver. The converter, managed by an adjustable responsibility cycle oscillator or microcontroller, supplies a separate energy provide with the required unfavourable bias. Adjusting the responsibility cycle permits management of the unfavourable bias’s magnitude. The DC-DC converter employs a capacitive coupling strategy, offering a easy answer with out the necessity for added voltage regulators or complicated designs. The configuration of such a gate driver with a DC-DC converter is proven in Determine 2, demonstrating Infineon’s compact design that may be mounted on a small card. This configuration permits optimistic and unfavourable biases for the gate driver of each high-side and low-side transistors. Offering adequate unfavourable bias successfully prevents false turn-on and ensures dependable operation. Infineon’s sub-card can ship as much as 3.5KW of energy, with PFC unit peak effectivity reaching round 99.3% and using isolation drivers for high-side and low-side.

[Figure 2: Schematic and physical design of the DC-DC converter with negative bias supply (source: Infineon Technologies)]

It must be famous that offering extra unfavourable gate bias could enhance margins and forestall false turn-on. Nevertheless, it would additionally enhance the diode voltage drop throughout the third-quadrant conduction. Thus, a stability have to be struck between offering adequate unfavourable bias and sustaining environment friendly operation.

Minimizing Energy Loop Inductance is the Last Step in Designing GaN Gate Drivers

Persson emphasised the usage of surface-mount packages to reduce energy loop inductance, as through-hole parts would want to function at decrease frequencies to mitigate overshooting of instantaneous inductance voltage. This limits GaN’s high-frequency capabilities, making surface-mount packages the popular selection, as seen in Infineon’s sub-card design in Determine 2. One other strategy is to concentrate to the course of present circulate to maximise the return present mutual inductance.

The gate driver present loop shares a standard inductance path with the primary present, which may be within the vary of a number of tens of amperes, and experiences altering present (dI/dt) via the trail’s inductance. This altering present induces voltage on the ends of the inductance, which might have an effect on the utilized gate voltage and decelerate turn-on and turn-off occasions. It could additionally trigger oscillation points and impression the general efficiency of the system. Subsequently, cautious design of the circuit structure and wiring can create a return path that maximizes mutual inductance and assists in designing environment friendly gate drivers for GaN power devices.