How can the performance of voltage regulators be improved in low voltage and high current applications?
As design requirements become increasingly challenging, especially in low-voltage, high-current applications such as data centers and AI, performance improvements in voltage regulators (VRS) are important. One possible performance improvement is to use coupled inductors, but a similar approach has recently been proposed in the industry, which is the trans-inductor voltage regulator (TLVR). The schematic of the TLVR is from the coupled inductor model, but the physical behavior is different. In fact, a simple model of a coupled inductor is often something that can be easily used in simulation to achieve the correct waveform, but it does not correspond to the actual physical behavior. TLVR, on the other hand, is built almost from the components shown in the schematic, so in this case the simulation model is closer to the physical behavior of the actual system.
TLVR is a relatively new development, and specific details and features are still being worked out. This article focuses on the transient behavior of TLVR, which affects the isolation requirements of the TLVR design itself, as well as the isolation and safety considerations of the entire motherboard.
TLVR and transients
The multiphase buck regulator uses the TLVR schematic from Figure 1. While the main inductor windings are still connected between the switching nodes of phase and VO, the added auxiliary windings are electrically connected in series with each other and to the tuning inductor LC. If the LC is removed, the circuit returns to having only the discrete (uncoupled) inductor in a buck converter. If the LC output is shorted, the correlation between the phases is strongest and transient performance is fastest, but this will also affect the current waveform and the general amplitude of the current ripple. In practice, LC is often a compromise between these two extremes.
Figure 1. TLVR schematic diagram
As with any multiphase buck converter, when a fast transient load step arrives, changes in output voltage cause feedback to react, adjusting voltage and current accordingly. For TLVR, one potential problem is that all auxiliary windings are connected in series, and the transformer turns ratio to the main winding is typically 1:1. There is a square wave applied at the switching frequency on the TLVR main winding, and ideally there is a temporal phase shift between the different phases. But during transients, these phases often align to improve performance.
Consider an aggressive ground load transient in a 12V to 1.8V application, all high side FETs in all phases are on to allow the inductor current to rise as fast as possible, so (VIN - VO) = 10.2V is applied to all mains simultaneously winding, as shown in Figure 2. The actual waveform will depend on the circuit parameters, but in the worst case, a 1:1 transformer will generate 10.2V on its secondary side, so the voltage pulse on the secondary side will be (VIN - VO) × NPH. This is obviously a security concern. Figure 2 gives actual values for a TLVR value of 150nH, with a small leakage inductance between the main and auxiliary windings measuring 5nH. The figure also shows an LC value of 160nH. This LS value is within the typical range of NPH~6, but can be adjusted, especially for different numbers of associated phases.
Figure 2. Equivalent schematic for TLVR = 150nH, worst-case loading transient
Figure 3. TLVR worst case transient simulation: a) LC = 160nH, b) LC open circuit, NPH = 20
Figure 3 shows a simulation for NPH = 20 with 100ns pulses at 10.2V for all VX switch nodes: LC = 160nH in Figure 3a and LC = open circuit in Figure 3b. All secondary TLVR voltage curves are plotted to show how the series connection of the windings gradually increases the voltage. When LC = 160nH and 20 secondary windings of associated phases are loaded, the voltage on the board reaches approximately 123V. But with the LC disconnected, the voltage step can be as high as 197V because there is no load on the secondary side. The total voltage is closer to worst case (VIN - VO) × NPH.
However, the results in Figure 3 are still too optimistic. In fact, the simplified simulation in Figure 3 requires at least the addition of parasitic capacitance between the GND plane and the fairly wide trace connecting the secondary TLVR winding. A realistic estimate of these parasitic capacitances is around 5pF. As shown in Figure 4, add a 5pF capacitor to each TLVR secondary node to obtain the simulation shown in Figure 5. The added parasitic capacitance causes a lot of oscillation in high-Q circuits because the resistance is kept to a minimum for efficiency and transient considerations. The same NPH = 20 case shows: when LC = 160nH is present, the voltage peak is 239V; if the LC is disconnected from the board, the peak voltage is 390V.
Note that the value of the layout parasitic capacitance is not important - it only affects the frequency and envelope of the oscillation, but not the amplitude.
Figure 4. Layout capacitor added to TLVR equivalent transient schematic
There are at least two ways to mitigate this high-pressure problem. One is to ensure that the phases are not aligned during the transient, or that no more than 2 or 3 phases are aligned. Controller designs can consider this approach, but obviously it will limit the speed achievable in the transient response. Another approach is to limit the number of TLVR associated phases. However, given that NPH needs to be high enough to constrain the current ripple, while NPH needs to be low enough to limit the worst-case secondary voltage, what are the practical limits of this approach?
Figure 5. TLVR worst-case transient simulation, adding 5pF capacitance to each secondary node: a) LC = 160nH, b) LC open circuit, NPH = 20
Considerations associated with NPH
A derivation of the current ripple in TLVR is as shown. It is valid for any duty cycle value, but since the equivalent circuit is simplified for this derivation (there is no dedicated leakage inductance LK as a separate component in each TLVR), it is accurate for LC = open circuit, but then it starts to accumulate The error reaches infinity when LC = short circuit. It also assumes that TLVR leakage inductance LK
Figure 6. Calculated normalized current ripple versus VO for different NPH (VIN = 12V): a) coupled inductor (LM/LK = 5), b) TLVR = 150nH (LC = 120nH)
Figure 7 shows the current ripple as a function of associated TLVR phase at TLVR = 150nH and different LC values. The lower the LC value, the greater the error introduced, but the trend is very clear; lowering NPH or lowering LC will cause the current ripple to increase. Note that TLVR always has more ripple than the baseline discrete inductor (LC = open circuit). Assuming that the LC value is large enough, it can be concluded that in order to keep the current ripple effect under control, the minimum number of associated phases should be around NPH_min~1/D, see equation (1). In other words, NPH should be raised to at least the first notch of the current ripple curve; here, the duty cycles of the different phases nearly overlap.
Figure 7. Calculated current ripple versus associated NPH for TLVR = 150nH at different LC (VIN = 12V, VO = 1.8V, fS = 400kHz)
Another conclusion is that the lower the VO, the higher the number of minimum correlation phases required, since NPH_min = VIN/VO. The TLVR solution requires approximately NPH_min~6 for VIN = 12V and VO = 1.8V, and approximately NPH_min~15 for VO = 0.8V, see Figure 8. Of course, a smaller number of NPH is acceptable if there is additional impact on current ripple and the reduction in efficiency can be tolerated. Note that for consistency, Figure 8 is plotted for the same TLVR = 150nH and the same LC value as the VO = 1.8V case. This results in smaller current ripples. However, reduced VO will make transient performance worse, so the TLVR solution will most likely be tuned to improve transients, resulting in increased current ripple.
Assuming that in a 12V to 1.8V application, targeting NPH = 6 can keep the TLVR current ripple low. Figure 9 shows the worst-case secondary TLVR voltage (VIN - VO) with 100ns pulses on all phases on the primary. When LC = 120nH is present, the secondary voltage can reach 77V. If the LC is disconnected from the PCB, the unloaded secondary voltage can oscillate up to 113V.
Figure 8. Calculated current ripple versus associated NPH for TLVR = 150nH at different LCs. VIN = 12V, VO = 0.8V, fS = 400kHz
Figure 9. TLVR worst-case transient simulation, adding 5pF capacitance to each secondary node: a) LC = 120nH, b) LC open circuit, NPH = 6
A rough estimate of the worst-case secondary TLVR voltage is shown in equation (2), where the 2x multiplier comes from the oscillation rather than the pulse waveform.
The internal leakage of the TLVR slightly reduces this voltage peak, but the leakage is generally small under design guarantees. Correspondingly, for NPH = 20, the estimated VPEAK is 408V; for NPH = 6, the estimated voltage peak is 122V, while the simulation results are 377V (Fig. 5b) and 113V (Fig. 8b) respectively.
In order to make the secondary voltage lower than the expected minimum VPEAK in the worst case, the estimated NPH_max is roughly as shown in Equation (3). Assuming the PCB's rated maximum limit is 60V, then for a 12V to 1.8V application, NPH_max
Figure 10 shows NPH_min (efficiency) and NPH_max (safety) versus VO, assuming safety ratings of VPEAK = 60V and VIN = 12V. Possible solutions between NPH_min and NPH_max only exist above VO = 3.5V, while at lower voltages NPH_MAX overrides it due to safety concerns, resulting in higher current ripple and associated efficiency impact.
Figure 10. NPH_min (efficiency) and NPH_max (safety) versus VO, assuming VIN = 12V, safety rating VPEAK = 60V
Of course, if NPH is reduced, this will also result in an increase in the total number of external tuning inductors LC, since one is required for each associated winding.
The TLVR method is an improvement over the discrete inductor solution, but it mainly improves the transient state and generates current ripple, thus worsening the efficiency. To keep the current ripple effect under control, it is recommended to associate NPH_min > VIN/VO. From a safety perspective, if the worst case voltage on the PCB is expected to be the VPEAK limit, then the number of associated phases needs to not exceed NPH_max
Another possibility to solve the high voltage problem is to ensure that the number of phases the controller is aligned to never exceeds the maximum number determined based on NPH_max above (the 60V limit is 2 to 3 phases at most, etc.). The challenge with this approach is that it limits how quickly the system's transient performance can respond. Excessive phase overlap during steady-state operation should also be considered.
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