I-NPC three-level circuit double pulse and short circuit test method
Author: Wei Zuoyu
Double-pulse testing (DPT) is a widely accepted method for evaluating the dynamic characteristics of power devices. Taking the application of IGBT in a two-level bridge circuit as an example, as shown in the figure below, by adjusting the DC bus voltage and the first pulse duration, the device under test can be captured at the end of the first pulse and the beginning of the second pulse. Switching transient behavior under any desired voltage and current conditions. DPT results quantify the switching performance of power devices and provide a reference for the design of power converters (such as determination of switching frequency and dead time, thermal management and efficiency evaluation). For three-level circuits, double-pulse testing is required How to do it?
Figure 1 Two-level typical DPT circuit
Figure 2 DPT typical test waveform
1. Commutation method and double pulse test method of I-NPC three-level circuit
First, let’s start with the working mode of the three-level bridge arm, taking the I-type NPC (Neutral Point Clamped) three-level circuit as an example:
Figure 3 I-NPC three-level bridge arm
Figure 4 I-NPC three-level bridge arm output voltage and current waveform
Figure 4 shows the waveforms of the output voltage and current of the I-NPC bridge arm in one power frequency cycle when the output power factor is zero. The phase difference between the two is 90 degrees. One cycle can be divided into ABCD segments, including the I-NPC circuit. Four commutation methods of work.
Period A (V>0, I>0) is the inverter working condition. The voltage and current directions are both positive (the current flowing out of the bridge arm is specified to be positive). The output level at the midpoint of the NPC bridge arm is between +Vdc and 0 at the switching frequency. Jump, T2 is normally open, T1 and D5 commutate, which is a small commutation loop as shown by the dotted line in Figure 5. During this period, there are conduction losses of T1, T2, and D5 and switching losses of T1 and D5.
To perform DPT for this working condition, the load inductor can be connected between the midpoint of the DC bus and the AC outlet terminal. T3 and T4 remain off, T2 remains on, and double pulses are applied to T1. After the first pulse arrives, the current flows Through T1, T2, and the load inductor, the current rises linearly. After the first pulse ends, T1 is turned off, and the inductor current continues to flow through D5 and T2. After the second pulse of T1 arrives, the current continues to flow through T1, T2, and the load inductor. , D5 is forced to turn off, and the test objects under this working condition are T1 and D5.
Figure 5 T1 and D5 commutation and DPT method
Period B (V>0,I
To perform DPT under this working condition, the load inductor can be connected between the positive end of the DC bus and the AC outlet end. T1 and T4 remain off, T2 remains on, and double pulses are applied to T3. After the first pulse arrives, the current flows Through the load inductor, T3, and D6, the current rises linearly. After the first pulse ends, T3 is turned off, and the inductor current freewheels through the anti-parallel diodes D1 and D2 of T1 and T2. After the second pulse of T3 arrives, the current continues to flow. Through the load inductance, T3, and D6, the anti-parallel diode D1 of T1 is forced to turn off. The test objects under this working condition are T3 and D1.
Figure 6 T3 and D1 commutation and DPT method
C period (V
Figure 7 T4 and D6 commutation and DPT method
Period D (V0) is symmetrical to period B, and is a rectifier operating condition. T3 remains on, T2 and D4 commutate, and the commutation loop is a large loop. During this period, there are conduction losses of D5, T2, D3, and D4 and switching losses of T2 and D4. The DPT method for this working condition is symmetrical to the B period working condition method. The load inductor is connected between the negative end of the DC bus and the AC outlet end, and the test objects are T2 and D4.
Figure 8 T2 and D4 commutation and DPT method
2. Double pulse actual measurement of I-NPC three-level circuit
Figure 13 shows the measured double-pulse waveform using Infineon's F3L400R10W3S7 EasyPACK™ 3B three-level module product. It can be seen that when the same current is turned off, the voltage peak of the inner tube in the long commutation circuit is significantly larger when it is turned off. Therefore, it is necessary to evaluate the voltage stress of the inner tube under severe working conditions through DPT during the design and application process, and optimize the peripherals. Stray inductance of the DC bus and power traces or adjusting peripheral drive parameters to improve the voltage stress of the inner tube and avoid device overvoltage failure.
Figure 13 F3L400R10W3S7 double pulse measured waveform
At the same time, DPT can also be used to quantify the size of the stray inductance of the two commutation circuits, as shown in the dotted line box in Figure 13. The drop of the voltage platform and the change rate of the corresponding current can be observed when the device under test is turned on for the second time in DPT to obtain It is found that the stray inductance of the short commutation loop is about 30nH, and the stray inductance of the long commutation loop is about 60nH.
For higher power systems, half-bridge modules are usually used to build three-level circuits. When constructing I-NPC three-level circuits, the scheme shown in the figure below is mainly used. Only one half-bridge is involved in short commutation conditions. module, a long commutation circuit will involve all three power modules. Therefore, in the power module design, the busbar design needs to be optimized to minimize the stray inductance of the long commutation circuit to increase the current output of the power module. ability. Figure 15 shows the measured double-pulse waveform of FF1800R12IE5 in the I-NPC circuit. Under room temperature and rated current conditions, in order to reduce the turn-off voltage peak of the long commutation circuit IGBT, a larger gate-level turn-off resistor is used. Finally, the maximum turn-off peak voltages of T1 and T2 are 1010V and 1100V respectively.
Figure 14 PrimePACK™ 3+ half-bridge module to build I-NPC three-level circuit
Figure 15 FF1800R12IE5 double pulse measured waveform
3. Short circuit test of I-NPC three-level circuit
For the short-circuit test of the I-NPC three-level bridge arm, the following recommended test conditions are given by simulating the short-circuit point position and actual driving timing (the inner tube is opened first and then closed):
・The AC point is short-circuited to DC+, which simulates a short-circuit when T3 is turned on, and the short-circuit current flows through T3 and D6;
・The AC point is short-circuited to DC-, simulating a short-circuit when T2 is turned on, and the short-circuit current flows through D5 and T2;
・The AC point and the DC midpoint are short-circuited, simulating a short-circuit when T1 or T4 is turned on, and the short-circuit current flows through T1, T2 or T3, T4;
・The DC midpoint and the upper bridge clamping point are short-circuited to simulate a short-circuit when T1 is turned on, and the short-circuit current flows through T1;
・The DC midpoint and the lower bridge clamping point are short-circuited to simulate a short-circuit when T4 is turned on, and the short-circuit current flows through T4;
・The AC point is short-circuited to the upper bridge or lower bridge clamping point to simulate a short circuit when the outer tube is turned on, and the short-circuit current flows through T1, T2, D6 or D5, T3, T4.
Figure 16 I-NPC three-level bridge arm short circuit test conditions
This article introduces several different commutation conditions of the I-NPC three-level circuit. Based on this, by adjusting the position of the inductor and the driving mode of the power device, the actual working conditions can be simulated to perform the corresponding double-pulse test. At the same time, it also gives For some measured waveforms of I-NPC circuit DPT, special attention needs to be paid to the optimized design of stray inductance of long commutation loops. Finally, some short-circuit conditions of I-NPC circuits are listed for your reference during testing. In the next issue, we will continue to analyze the double pulse test and short circuit test evaluation of the T-NPC circuit.
#INPC #threelevel #circuit #double #pulse #short #circuit #test #method
- High-speed current impact test system facilitates efficient testing of new energy vehicle wiring harnesses
- Area array CCD structure diagram and working process analysis
- Input-output relationship and circuit application diagram of voltage follower
- How to keep driving heavy loads when the voltage drops?
- Novel theory-based evaluation gives a clearer picture of fusion in the sun
- What are the disadvantages of IC temperature sensors?
- Control transformer overcurrent protection, grounding and applications
- What is the difference between chip packaging and SMD?
- Design and application of dry multi-channel priority amplifier
- Can igbt directly replace thyristor? What will be the impact of IGBT directly replacing thyristor?