LDO Basics: Noise
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LDO Basics: Noise

Posted Date: 2024-01-20

In an LDO Basics blog post, I discussed using low dropout regulators (LDOs) to filter the ripple voltage caused by switch-mode power supplies. However, this is not something to consider when getting a purified DC power supply. Because LDOs are electronic devices, they generate a certain amount of noise themselves. Choosing to use a low-noise LDO and taking steps to reduce internal noise can form an integral part of cleaning up the power rails without compromising system performance.

Identify noise

The ideal LDO has a voltage rail with no AC components. But the disadvantage is that LDO generates body noise like other electronic devices. Figure 1 shows how this noise behaves in the time domain.

Output noise (100μV/p)

Figure 1: Output noise snapshot of a noisy power supply

Analysis in the time domain is difficult. Therefore, there are two main ways to examine noise: across the entire spectrum, and as a composite value.

You can use spectrum analysis tools to identify various AC components in the LDO output line. (The application, "How to Measure LDO Noise," provides a wealth of noise measurement knowledge.) Figure 2 plots the output noise of the 1A low-noise LDO TPS7A91.

Noise (μV√Hz)

Frequency(Hz)

Figure 2: TPS7A91 noise spectral density vs. frequency and VOUT

As you can see from the various plots, the output noise (expressed in hertz per square root[μV/Hz]) is concentrated at the low end of the spectrum. Most of this noise comes from the internal reference voltage, as well as the error amplifier FET and resistor divider.

Analyzing the output noise across the entire frequency spectrum can help us determine the noise curve for the noise range of interest. For example, audio application designers are concerned about the audible frequencies (20Hz to 20kHz), and power supply noise can degrade sound quality.

When comparing Apple devices, datasheets often provide a single, combined noise value. The output noise is generally a comprehensive noise from 10Hz to 100kHz, expressed in microvolt root mean square (μVRMS). (Manufacturers will also synthesize noise from 100Hz to 100kHz, or synthesize noise from a custom frequency range. Synthesis based on the selected frequency range can help mask undesirable noise attributes, so check for values ​​other than the synthesis value. The noise curves are important.) Figure 2 shows the combined noise values ​​for each curve. The LDO series supplied by Texas Instruments has an integrated noise value as low as 3.8μVRMS.

Noise reduction

In addition to selecting an LDO with low noise quality, there are several techniques you can employ to ensure that your LDO has noise characteristics. These techniques include the use of noise reduction and feedforward capacitors. I will explore using feedforward capacitors in my next blog post.

Noise reduction capacitor

Many of TI's low-noise LDO families have dedicated pins dedicated to "NR/SS" as shown in Figure 3.

VOUT= VREFx (1+R1/ R2)

to load

ground

VIN

VBIAS

VREF

Figure 3: NMOS LDO with NR/SS pins

This pin has two functions: it is used to filter noise from the internal reference voltage, and to reduce the slew rate during startup or enable the LDO.

Adding a capacitor (CNR/SS) to this pin creates an RC filter with internal resistance that helps shunt unwanted noise generated by the reference voltage. Since the reference voltage is the main source of noise, adding the capacitor pushes the cutoff frequency of the left low-pass filter. Figure 4 shows the effect of this capacitor on output noise.

none

Noise (μV√Hz)

Frequency(Hz)

Figure 4: TPS7A91 Noise Spectral Density vs. Frequency and CNR/SS As shown in Figure 4, higher CNR/SS values ​​will produce more ideal noise values. After a certain point, increasing the capacitor value no longer reduces the noise. The remaining noise comes from error amplifiers, FETs, etc.

Adding the capacitor also creates a resistor-capacitor delay during startup, which will cause the output voltage to rise at a slower rate. When large capacitance is present in the output or load, it is beneficial to reduce the starting current.

The starting current in Equation 1 is equal to:

(1)

To reduce startup current, you must reduce the output capacitance or reduce the slew rate. Fortunately, CNR/SS helps achieve the latter, as shown in Figure 5 for the TPS7A85.

time (ms)

Voltage(V)

Figure 5: TPS7A85 startup vs. CNR/SS

As you can see, increasing the CNR/SS value increases the startup time, preventing spikes in startup current and potentially triggering the current limit.


#LDO #Basics #Noise