Multi-core heterogeneous design and communication solutions for Renesas RZ/G2L MPU
This article introduces the multi-core heterogeneous design and communication solution of Renesas RZ/G2L MPU.
In today's industrial and consumer electronics applications, system requirements are increasingly demanding not only the execution of complex control tasks, but also the need to collect and process data in real time. To meet these demands, multi-core heterogeneous processors have become a popular solution. This type of processor usually combines the ARM architecture's A-series cores (for handling advanced computing tasks) with M-series or R-series cores (focused on real-time operations). Under this architecture, complex control tasks can be processed by the A core equipped with Linux, while the collection and processing of real-time data can be completed by the M core or R core running RTOS or bare-metal.
Compared with the traditional multi-chip system design of single-core MPU and single-core MCU, multi-core heterogeneous processors show significant advantages. In traditional designs, a large amount of data needs to be exchanged between two chips through an external interface, which not only takes up valuable pin resources, but also results in low data transmission efficiency. On the contrary, multi-core heterogeneous processors integrating A core and M core or R core use the internal bus structure to achieve fast communication and share internal resources, thus avoiding the occupation of external pins. This multi-core heterogeneous system design not only reduces information security risks in the communication process, but also reduces chip procurement and management costs, reduces the cost and size of PCB boards, and simplifies the development process.
RZ/G2L product introduction
General-purpose microprocessor equipped with dual-core Arm Cortex-A55 (1.2 GHz) CPU and single-core Arm Cortex-M33 (200 MHz) CPU, 3D graphics acceleration engine and video encoding and decoding engine.
G2L block diagram
Heterogeneous communication mechanism OPENAMP
Open Asymmetric Multi-Processing
In the RZ/G2L series of MPUs, we can see a practical application of multi-core heterogeneous architecture. This MPU has a large core Cortex-A55 with a frequency of up to 1.2GHz, capable of running the Linux operating system, and a small core Cortex-M33 with a frequency of 200MHz, designed to run RTOS or bare-metal (bare-metal) programs. Heterogeneous communication between these two cores is achieved through the OpenAMP software framework.
OpenAMP is a lightweight communication protocol that enables different processors to communicate through shared memory or message passing mechanisms. In a multi-core processing system, each processor may run different software modules, and the OpenAMP framework provides an effective means for data exchange and collaboration between these modules. In this way, OpenAMP not only simplifies communication between multi-processors, but also enhances the collaborative efficiency and functionality of the entire system. see picture 1.
Virtio is a virtual device framework for shared memory management. The vring in Virtio is a FIFO queue pointing to the data buffer pointer. There are two one-way vrings, one vring is dedicated to messages sent to the remote processor, and the other vring is used to The data received from the remote processor is stored in shared memory, namely Vring buffers, half of which is used for sending and half for receiving.
remote handler messaging
The RPMsg framework is located on the upper layer of Virtio. The RPMsg (Remote Processor Messaging) framework is a message bus based on Virtio. See Figure 2.
The Linux operating system on the main processor can perform life cycle management of the remote processor and its related software environment, that is, starting or shutting down the remote processor. See Figure 3.
IPCC Inter-Processor Communication Controller
MHU (Message Handling Unit) is an IP module in the MPU chip, which plays the role of IPCC and is used for message communication between Cortex-A55 (CA55) or with Cortex-M33 (CM33). Data transfer is implemented through shared memory.
A channel consists of a pair of data transmission processing registers and response transmission processing registers, with a total of 12 channels (CA55 Core0/Core1 CM33, safe and non-safe areas) mounted. See Figure 4.
The above introduces the RZ/G2L dual-core heterogeneous communication method, and RZ/G2L products also provide corresponding software support.
Multi-os (CA55 Linux + CM33 RTOS)
Customers can quickly develop applications using Flexible Software Packages (FSP) and use OpenAMP to create applications that work with Linux. See Figure 5.
Cortex-M33 development environment
The corresponding hardware boards and software tools can be obtained through the Renesas official website.
JTAG online debugging
When connecting to JTAG, DIP SW1 must be set as follows. See Figure 7.
CORTEX-M33 startup method
● CM33 is loaded and started by CA55
● There are several points in the boot process when you can do this:
● Arm Trusted Firmware
The fastest way to start CM33
Allows code to be loaded into secure RAM
● u-boot -> Multi OS SW package default mode
CM33 firmware is easy to update
Binaries are stored in a file system accessible to u-boot
● Linux (remoteproc)
The most convenient maintenance, with few software upgrade changes
When sharing resources, please pay attention to the following allocations
● Pin multiplexing
● Memory allocation
● Peripheral allocation
The above introduces the multi-core heterogeneous design and communication solution of RZ/G2L MPU. Currently, the RZ/G series adopts the multi-core heterogeneous design of ARM A core and M core or R core. For more product information, you can visit the Renesas official website.Review Editor: Tang Zihong
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