PCB stacked structure and impedance calculation notes sharing
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PCB stacked structure and impedance calculation notes sharing

Posted Date: 2024-01-26

1. PCB stack structure and impedance calculation

1.1. Core and PP

PCB is composed of Core and Prepreg (preg).

Core is a copper-clad laminate (usually FR4 - fiberglass & epoxy resin), and the upper and lower surfaces of the Core are filled with solid materials;

Common prepreg types:106,1080,2313,3313,2116,7628

PP original thickness:7628 (0.185mm/7.4mil), 2116 (0.105mm/4.2mil), 1080 (0.075mm/3mil), 3313 (0.095mm/4mil)

Actual thickness after pressing is completed:Usually it will be about 10-15um smaller than the original value.

Commonly used copper thickness:1/3oz, 1/2oz, 1oz, 2oz

1.2. PCB stacking mechanism and impedance design

1.2.1. Prerequisites for laminated structure design

1.2.2. Stacked structure and impedance design process

(1) Arrangement order of signal layer, ground layer, and power layer (comparison of 2 types of stacking)

a. Analysis of Structure 1

The power layer is adjacent to the ground layer and is close to each other, which can achieve good coupling between the power supply and the ground.

Signal layer 3 is adjacent to the ground layer and uses the complete ground layer as the reference plane, so the signal integrity is the best.

Signal layer 2 is adjacent to the power layer. If the power layer is a complete plane, better signal integrity can also be obtained. However, if there is more than one type of power supply, the power layer needs to be divided into blocks. The incomplete reference plane will As a result, the signal return path is blocked, which has a certain impact on signal integrity.

Signal layers 1 and 4 are adjacent to signal layers 2 and 3 and are easily affected by adjacent signal layers, so the integrity is the worst.

b. Analysis of Structure 2

The power layer and the ground layer are not adjacent, and the coupling is poor, so effective small parasitic capacitance cannot be formed.

The adjacent layers of signal layers 1, 2, 3, and 4 can find the ground layer or power layer as the reference plane. The signal quality is better than that of structure 1. Among them, signal layers 1 and 4 are located on the surface layer, and the impedance control of the surface layer is better than that of the inner layer. Disaster. Therefore, in terms of signal integrity, signal layers 2 and 3 are better than 1 and 4.

(2) Line width and layer thickness

a. Change the reference layer thickness from 0.1mm to 0.2mm, and the impedance increases from 47Ω to 67Ω

b. Change the line width from 0.2mm to 0.3mm, and increase the impedance from 67Ω to 53Ω

(3) Example of stacked structure and impedance design (16-layer board, maximum signal frequency 400MHz)

a. Determination of prerequisite parameters

Number of veneer layers:8 signal layers, 3 power layers, 3 ground layers, 2 surface layers (device + signal)

Veneer thickness:2mm

Target impedance:Single-ended signal 55±15Ω, differential signal 100±15Ω

Material selection:FR4, Er=4.2, tanδ=0.002

b. Stacked structure and impedance design

Stacking characteristics: The PCB stacking structure is completely symmetrical in terms of material and thickness.

Determine the thickness of each layer and select Core, PP and Cu correctly:

5*Core1: 0.69+0.69+3.94 mil=5.32 mil

2*Core2: 0.69+0.69+5.9 mil=7.28 mil

6*PP1: 3.94 mil

2*PP2: 5.9 mil

Cu: 0.69 mil

Total thickness: 5*Core1+2*Core2+6*PP1+2*PP2+2*Cu=77.98 mil = 1.98 mm

After determining the thickness of each layer, calculate the signal trace width of each layer:

surface single-ended signal

Inner single-ended signal

Inner layer differential signal (SI9000 calculation)

c. Determination of power layer and ground layer

The stacking has determined the position of the power layer or ground layer. This step determines whether the second, fifth, eighth, ninth, twelfth, and fifteenth layers correspond to the power layer or the ground layer.

Eighth, the ninth layer is located in the center of the PCB and is closely adjacent. One layer is used as the power layer and the other layer is used as the ground layer, which can achieve a good coupling effect.Considering that the power plane of the power supply layer that needs to be divided (shared by four power supplies) is fragmented and needs to be coupled with a complete ground plane, it can be determined that the eighth layer is the ground layer and the ninth layer is the divided power layer;

Second, the fifteenth layer is directly adjacent to the surface layer. From the perspective of EMC, it should be selected as the ground layer;

The fifth and twelfth layer are used as 2.5V and 3.3V power planes.

After determining the power layer and ground layer, you need to formulate the following rules for the signal layer accordingly:

The main reference plane of the tenth layer is the ninth layer, and the ninth layer is a divided power layer, which has a greater impact on signal return. Therefore, it is not recommended to use high-speed signals on the tenth layer.For some non-important signals, such as control signals, JTAG signals, etc., due to their weak impedance control requirements, they can be placed on the tenth layer.

The main reference plane of the seventh layer is the eighth layer. The eighth layer is a complete ground plane, which can provide a good return path for the seventh layer. However, the filling material between these two layers is PP. After the PCB is made, There may be certain deviations in impedance control.Therefore, the seventh layer can carry high-speed signalsbut for some very critical high-speed signals, such as the differential pair bus SPI4.2 with a speed of 400MHz on a single board, it is not recommended to go on the seventh layer.

The main reference plane of the third layer is the second layer, and the second layer is a complete ground plane, and the solid material is used to fill the two layers. The impedance control is better, and it is suitable for carrying high-speed key signals. Similarly, the fourteenth The layer is also suitable for carrying high-speed critical signals.

The main reference plane of the fourth layer is the fifth layer. The fifth layer is a complete 2.5V power plane. The space between the two layers is filled with solid material to route high-speed key signals on the fourth layer.In this design, there are a large number of DDR SDRAM interface signal lines. Among them, the address and control signals of DDR SDRAM are all based on 2.5V. It is recommended that these signals are also routed on the fourth layer.

The main reference plane of the 13th layer is the 12th layer. The 12th layer is a complete 3.3V power plane. The space between the two layers is filled with solid material. High-speed key signals can go on the 13th layer.at the same time, it is recommended that many single-ended signals powered by 3.3V, such as clock signals, etc., be routed on the thirteenth layer.

Sixth, the main reference planes of the eleventh layer are the fifth and twelfth layers respectively. The space between them and the reference planes is filled with PP. There may be deviations in the impedance control. Therefore, high-speed signals can be routed on these two layers, but it is not recommended. Very critical high-speed signals.

When designing, it should be noted that the third and fourth layers, the sixth and seventh layers, the tenth and eleventh layers, the thirteenth and fourteenth layers are adjacent to each other and may interfere with each other. Therefore, when walking When wiring, adjacent signal layers should be routed orthogonally. If the wiring direction of the third layer is horizontal, the wiring direction of the fourth layer should be vertical.

[The above information is compiled and released by Aibo Testing. If there is any discrepancy, please correct it in time. If there is any reference, please indicate the source. Welcome to discuss together. We have been paying attention to its development! Focus on: CCC/SRRC/CTA/operator warehousing]

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