Reliability Assessment of SiC MOSFETs Under Repeated UIS Stress

Silicon carbide (SiC) units, as a consequence of their superior efficiency, are notably appropriate to be used in high-power, high-temperature, and high-switching-frequency purposes. Lately, important progress has been made within the improvement of SiC units, particularly when it comes to their reliability, making SiC-based units a viable different to silicon-based energy units.

Nonetheless, even with these developments, SiC units nonetheless face reliability points in some excessive working situations comparable to overcurrent, overtemperature, quick circuits, and non-clamped inductive switching, which hinder their full substitute of silicon-based units.

For example, electrical motors expertise sudden excessive present and voltage pulses throughout startup or load variations. Regardless of well-designed inverters or energy provides, parasitic inductances within the circuit can result in excessive voltage spikes. These voltage spikes can simply exceed the utmost breakdown voltage, inflicting avalanche breakdown in a brief interval. This stress can result in parameter drift, limiting the operational vary and lifespan of the elements.

The system beneath take a look at is linked to the facility provide by means of inductors and high-speed switches. When the swap is closed to provoke system operation, the present begins to rise linearly. Upon reaching the predetermined experimental present, the system is turned off together with the swap.

The magnetic subject within the inductor generates a again electromotive pressure (EMF), leading to a really excessive voltage throughout the system. With out protecting circuits in place, all of the vitality saved within the inductor will get discharged instantly into the system.

Determine 1: UIS Check Circuit

Typical UIS Curve for SiC MOSFET

Measurements of system traits earlier than and after every pulse sequence reveal the gradual affect of repeated UIS stress. After present process tens of millions of pulse cycles, the comparability of I-V curves for the system earlier than and after stress is proven in Figures 3 and 4.

Determine 3: Drain-Supply Voltage I-V Curve

Determine 4: Supply-Drain Voltage I-V Curve

Repeated UIS pulses trigger a slight drift in threshold voltage and result in a lower in on-state resistance, which is clear within the output traits. The discount in on-state resistance signifies that the traits are unaffected by thermal biking.

In the course of the avalanche part of UIS pulses, numerous high-energy cost carriers are generated close to the blocked PN junction. The drift in threshold voltage means that optimistic fees are trapped on the channel-gate interface or close by. The origin of those optimistic fees could be attributed to the formation or activation of electrically energetic defects within the gate dielectric attributable to the formation of high-energy holes through the UIS pulse course of.

Adjustments in drain present traits are induced by a rise in electrically energetic lure density, manifested as a rise in drain present itself and a change within the form of the I-V curve, probably as a consequence of adjustments in cost distribution and ensuing electrical subject distribution.

Repetitive avalanche stress considerably impacts {the electrical} efficiency of the examined system. After present process repeated UIS stress exams, the system reveals a constant degradation pattern, characterised by a lower in threshold voltage, discount in on-state resistance, and a big improve in drain-source and gate-source leakage currents. Extended repetitive UIS stress additionally notably will increase the turn-on time.

Therefore, in addition to typical reliability issues, SiC MOSFETs require specialised testing approaches primarily based on the distinctive traits of SiC to successfully assess their reliability.