RZ/T RZ/N series schematic design considerations
a power supply
Power on and off timing scheme:
Two reset circuits
The chip has 2 reset signals:
RES resets LSI peripherals other than the emulation circuit, so the reset of the emulator needs to be connected to this signal.
TRST resets TAP (Test Access Port). The emulator reset pin cannot be connected here, otherwise it cannot be simulated. When this pin is not used, it can be connected to ground through a pull-down resistor, or connected to the same signal as RES. Be careful not to leave it floating.
There are 2 reset signals on the emulator side:
nSRST system reset must be connected. The system can be reset through the debugger to facilitate debugging.
nTRSTTAP is reset and can be left unconnected.
The wiring diagram is as follows:
Three parallel ports
When using only one SDRAM, only CS3 can be used, and CS2 cannot be used alone.
Four network peripherals
ECAT: It is recommended to use the MII interface, with small address IN and large address OUT. The addresses need to be consecutive. Address 0 is generally not used.
LED1, PHYAD(1), ETHn_LINK, three signals are multiplexed on the same pin, so the following operations need to be done:
①The status of the LED needs to be kept in a stable state, that is, it cannot be made to flash.
Change the PHY register to 0x30. When sending and receiving packets, the LED will be on. When it is down, the LED will be off.
The register corresponding to LEDO is ext Reg0x40C0; (the power-on default value is 0x0311)
The register corresponding to LED1 is ext Reg0x40C2; (the power-on default value is 0x0320)
Assigning different values to these two registers, the LED will display the corresponding status. Typical configurations are as follows:
ext Reg0x40C0/0x40C3 configuration value
When the link is at 10M, the LED lights up; when the link is at 10M and packets are sent and received, the LED flashes.
When the link is at 100M, the LED lights up; when the link is at 100M and packets are sent and received, the LED flashes.
When link or sending and receiving packets, the LED is on; when link is down, it is off.
It flashes when sending and receiving packets; it goes off when not sending and receiving packets.
②The LED of YT8512 has the function of automatically detecting the external pull-up and pull-down status to determine whether the LED is valid. The polarity of the MPU link must be determined accordingly, otherwise the network will repeatedly link-up and link-down.
If the PHYAD(1) address of the PHY is 1, LED1 is externally pulled up, and when the LED1 signal is low, the light turns on. At this time, you need to configure the polarity PHYLNK.CATLNK of the MPU's link detection status to be low, that is, if a low level is detected, it is judged to be a link, and the LED is on.
If the PHYAD(1) address of the PHY is 0, LED1 is externally pulled down, and when the LED1 signal is high, the light turns on. At this time, you need to configure the polarity PHYLNK.CATLNK of the MPU's link detection status to be high, that is, when a high level is detected, it is judged to be a link, and the LED is on.
YT8512 has two LED pin outputs, which are pin24-LED0 and pin24-LED1. Both pins have weak pull-down resistors internally.
In addition to being used as LED output pins, they are also used as PHY address configuration pins during the Power on Strapping stage, so sometimes these two pins have strong external pull-ups or strong pull-downs (4.7k).
The output polarity of the LED pin (that is, active high or active low) is related to the pull-up resistor or pull-down resistor connected to the pin. (If there is an external pull-down resistor, the external pull-down resistor shall prevail. If there is no external pull-up and pull-down resistor, the internal default pull-up and pull-down resistor shall be relied upon.)
If there is a pull-up resistor, it is active low (that is, the cathode of the external LED light is required); if there is a pull-down resistor, it is active high (the anode of the external LED light)
a pull-up, sink mode
b drop-down, source mode
①A transformer between the PHY and the RJ45 connector is necessary. Some RJ45s integrate the function of a transformer, which can simplify the circuit.
②Receive the reference clock from the MAC or output the reference clock to the MAC. If the reference clock is output to the MAC, the 25MHz crystal/clock source should be connected to the PHY
③The total deviation of the transmitter clock frequency is specified by IEEE 802.3u as ±100PPM (±50PPM is preferred)
④Check whether MDIO requires an external pull-up resistor
⑤Consider adding a series terminal resistor near the signal source to reduce reflections on the signal line
①The impedance of RMII/MII is 50 ohms ±10%, which is the normal standard for most wiring.
②All MII/RMII signal lines (data lines, clock lines and others) are routed on a single layer with precise length matching
The trace length deviation of data lines and clock lines should be within 10mm
Through holes should be avoided
③The MII/RMII signal path should be as straight as possible, and the shorter, the better. Otherwise, the trajectory bend should not exceed 45 degrees.
④Keep the clock signal wiring as short as possible. When special circumstances require longer wiring, it must be shielded by the ground wire.
⑤ Place a ground layer below or above the signal layer so that the return current of the MII/RMII signal can return at any time
Since the MPU is the master, the CLK signal is sent by the master, and DATA is fed back from the device. If the trace is too long and comes back again and again, the DATA returned at this time may have a phase difference compared with the CLK sent by the MPU, causing data misalignment. Therefore, the common approach is to get the clock signal through another clock signal line. .
1 Try to use an active crystal oscillator, connect EXTAL to VSS, and keep XTAL open circuit.
2. Use a passive crystal oscillator. The crystal oscillator and capacitor should be as close as possible to the EXTAL and A distance of 0.3 mm ~ 2.0 mm should be maintained.
Seven MDV pins
MDV0~MDV2 correspond to ETH0~ETH2. Select the corresponding 1.8V or 3.3V according to the actual PHY chip.
MDV1 and ESC_LEDRUN, MDV2 and ESC_LEDERR pins are multiplexed:
If MDV needs to be connected to a pull-up, without special processing, LEDRUN and LEDERR may light up when the ESC module does not come up at the moment of power-on. Until the ESC module controls these two pins, they can light up in the normal state. To avoid this situation, you can handle it according to the following hardware methods.
MDV3~MDV4 correspond to XSPI0 and XSPI1, which are determined according to the type of externally configured memory chip.
The MDD pin is always low.
Review Editor: Tang Zihong
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