Semiconductor back-end process Part 4: Understanding different types of semiconductor packaging (Part 2)
In the third article of this series, we introduced traditional packaging and wafer-level packaging. This article will continue to introduce packaging technology that integrates multiple packages and components into a single product. Among them, we will focus on packaging stacking technology and system-in-package (SiP) technology, both of which help reduce packaging volume and improve packaging process efficiency.
1. Stacked Packages
Imagine that a housing complex consisting of several low-rise buildings would require a very large area to accommodate thousands of residents. However, a skyscraper can accommodate the same number of residents. This example clearly illustrates one of the advantages of stacked packaging. Compared with products that have multiple packages distributed horizontally over a larger area, products composed of stacked packages can further improve performance while reducing volume. In addition to being an important packaging technology, stacked packaging is also a fundamental method used in product development.
In the past, products often contained only one chip in a package, but now it is possible to develop multi-chip packages that cover many different functions or integrate multiple memory chips into a single package with higher capacity. In addition, system-in-package integrates multiple system components into a single package. The advent of these technologies enables semiconductor companies to meet diverse market demands while creating high value-added products.
Figure 1: Classification of stacked packaging methods (ⓒ HANOL Press)
As shown in Figure 1, stacked packages can be divided into three major categories based on different development technologies: 1) package stacks formed by vertically stacking packages; 2) stacking different chips in a single package using wire bonding technology Chip-on-chip packaging; and 3) using through silicon vias (TSV)1It is a chip stack packaging technology that replaces traditional wire bonding technology to achieve internal electrical interconnection. Each stacked packaging technology has different characteristics, advantages and limitations, which will determine their future applications.
1 Through Silicon Via (TSV, Through Silicon Via): A vertical interconnect channel that can completely pass through a silicon die or wafer to achieve stacking of silicon wafers.
Package stacking is accomplished by stacking packages vertically. Therefore, its advantages and disadvantages are exactly opposite to those of chip stack packaging. The package stacking method stacks tested packages on top of each other so that if a package fails the test, it can be easily replaced with a functional package. Therefore, its test yield is higher than that of chip stack packaging. However, the package stack size is larger and the signal paths are longer, resulting in electrical characteristics that may be worse than those of chip-on-chip packages.
One of the most common packaging stacking technologies is package-on-package (PoP), which is widely used in mobile devices. For stacked packages for mobile devices, the chip types and functions used for the upper and lower packages may be different and may come from different chip manufacturers.
Typically, the upper package mainly includes memory chips produced by semiconductor memory companies, while the lower package contains chips with mobile processors, which are designed by fabless design companies and outsourced by wafer foundries and outsourcers. Semiconductor Assembly and Test (OSAT) facility production. Since the packages are produced by different manufacturers, quality inspection is required before stacking. Even if a defect occurs after stacking, the defective package simply needs to be replaced with a new one. Therefore package stacking has greater benefits at the commercial level.
Chip Stacks - Chip Stacks With Wire Bonding
When multiple chips are packaged in the same package, the chips can be stacked vertically or connected horizontally to the circuit board. Vertical stacking is the preferred method because horizontal layout can lead to oversized packages. Compared with package stacking, the chip stacking package size is smaller and the electrical signal transmission path is relatively shorter, so the electrical characteristics are better. However, if a chip is found to be defective during testing, the entire package is scrapped. For this reason, the test yield of chip stack packages is low.
In chip stacking packaging, if you want to increase the memory capacity, you need to stack more chips in a single package. As a result, technology that can integrate multiple chips into the same package emerged. But at the same time, people do not want the package thickness to become thicker as the number of stacked chips increases, so efforts are being made to develop technology that can limit the package thickness. To do this, it is necessary to reduce the thickness of all components that may affect the package thickness, such as chips and substrates, while also reducing the gap between the uppermost chip and the upper surface of the package. This brings many challenges to the packaging process, because the thinner the chip, the more susceptible it is to damage. Therefore, current packaging processes are working to overcome these challenges.
Through Silicon Via (TSV) - Chip Stacks With TSV
Through silicon vias are a chip stacking technology that involves drilling holes into silicon wafers to accommodate electrodes. Compared with using traditional wire methods to achieve chip-to-chip interconnection or chip-to-substrate interconnection, through silicon vias are achieved by drilling holes on the chip and filling them with conductive materials such as metal. Chips are interconnected vertically. Although chip-level processes are used for stacking using through-silicon vias, wafer-level processes are used to form through-silicon vias and solder bumps (Solder Bumps) on the front and back of the chip. As a result, through silicon vias are classified as wafer-level packaging technology.
Figure 2: Cross-sectional view of a chip using through silicon via technology (ⓒ HANOL Press)
The main advantages of TSV packaging are superior performance and smaller package size. As shown in Figure 2, a chip stack package using wire bonding utilizes wires to connect to the sides of each stacked chip. As the number of stacked chips and connecting pins increases, the leads become more complex and more space is required to accommodate them. In contrast, TSV chip stacking does not require complex wiring, resulting in smaller package sizes.
As introduced in the previous article, flip chip packaging (Flip Chip) has good electrical characteristics for the following reasons: it is easier to form input/output (I/O) pins at ideal locations; the number of pins increases; The signal transmission path is shorter. For the same reason, TSV packages also have good electrical properties. When sending electrical signals from one chip to the chip below it, through-silicon via packaging enables the signals to travel directly downward. In contrast, with a wire-bonded package, the signal travels down to the substrate and then up to the chip, resulting in a much longer signal path. In the leaded chip stack shown in Figure 2, no lead connection can be made at the center of the chip. In contrast, through-silicon via packages drill holes in the center of the chip to form electrodes and connect to other chips. Unlike wire connections, through-silicon via packaging can significantly increase the number of pins.
High-bandwidth memory (HBM) uses a new DRAM architecture that uses through-silicon via technology to increase the number of pins. Usually, in DRAM specifications, "X4" means that there are four pins used to send information, or that 4 bits of information can be sent from the DRAM at the same time. Correspondingly, X8 means 8 bits, X16 means 16 bits, and so on. Increasing the number of pins facilitates sending more information simultaneously. However, due to its own limitations, lead chip stacking can only reach x32 at most, while through silicon via stacking has no such limitations, allowing HBM to reach x1024.
Currently, through-silicon via packaging is used for mass-produced memory products of DRAM, including HBM and 3D stacked memory (3DS). The former is used in graphics, networking and high-performance computing (HPC) applications, while the latter is primarily used as a DRAM memory module.
Figure 3: 2.5D packaging using HBM (ⓒ HANOL Press)
HBM is not a fully packaged product, but a semi-packaged product. When the HBM product is sent to the system semiconductor manufacturer, the system semiconductor manufacturer uses an interposer 2 to build a 2.5D package 3 that arranges the HBM side by side with the logic chip, as shown in Figure 3. Since the substrate in the 2.5D package cannot provide pads to support all the input/output pins of the HBM and logic chips, an interposer is required to form the pads and metal wiring to accommodate the HBM and logic chips. These interposers are then connected to the substrate. These 2.5D packages are considered a system-in-package.
Products that also use through-silicon via packaging include 3DS DRAM, which is a memory module with a ball grid array (BGA) 4 mounted on a PCB board. Although DRAM memory modules in servers require high-speed transmission and large-capacity storage, chip stack packaging using wire bonding cannot meet these requirements due to its speed limitations. For this reason, high-end systems such as servers often use modules composed of through-silicon via chip stack packages.
2Interposer: A wide and fast electrical signal pipeline between die in a 2.5D configuration.
3 2.5D package: 2.5D and 3D packages contain multiple integrated circuits in each package. In the 2.5D structure, two or more active semiconductor chips (Active Semiconductor Chips) are arranged side by side on a silicon interposer. In a 3D structure, active chips are integrated by stacking the die vertically.
4 Ball Grid Array (BGA): A surface mount chip package that uses solder balls as its connectors.
2. System-in-Package (SiP)
The package composed of HBM and logic chip belongs to system-level packaging. As the name suggests, system-in-package refers to the integration of a system in a single package. However, a complete system also needs to include components such as sensors, analog-to-digital (A/D) converters, logic chips, memory chips, batteries, and antennas. However, at the current level of technological development, it is not yet possible to integrate all these system components. into a single package. Therefore, researchers are working to continuously develop packaging technologies for this area, and current system-in-package refers to integrating some system components in a single package. For example, HBM packaging is used to integrate HBM and logic chips into a single package to form a system-in-package.
Unlike system-in-package, system-on-a-chip (SoC) implements system functions at the chip level. In other words, multiple system functions are implemented on the same chip. For example, most current processors integrate static RAM (SRAM) memory into the chip, which can simultaneously implement the logic functions of the processor and the storage functions of SRAM on a single chip. Therefore, these processors are classified as system-on-a-chip.
System-on-a-chip requires combining multiple functions into a single chip, so the development process is complex and lengthy. In addition, if you want to upgrade the functions of individual components in a developed system-on-chip, you need to design and develop them from scratch. System-in-package is easier and faster to develop because system-in-package is achieved by integrating multiple developed chips and devices into a single package. Because the chips themselves are developed and manufactured separately, it is easy to integrate the devices into a single package even if their structures are completely different. At the same time, if only one aspect of functionality needs to be upgraded, the newly developed device can be integrated within the chip without developing the package from scratch. However, if the product will be used in large quantities for a long time, it will be more efficient to develop it as a system-on-chip than a system-in-package, because system-in-package requires more materials to be manufactured, which will increase the package volume. Only in this way can Consolidate multiple chips into a single package.
Despite the various differences between system-on-a-chip and system-in-package, the two are not an either-or relationship. In fact, the two can be combined to create a synergistic effect. After the system-in-a-chip is developed, it can be packaged into a single package with other functional chips and then implemented as an enhanced system-in-package.
Figure 4: Comparison of signal transmission path lengths between system-on-chip and system-in-package using through silicon via stacking (ⓒ HANOL Press)
When comparing the performance of system-in-package and system-on-a-chip, people originally thought that the system-in-a-chip would be implemented on a single chip and therefore its electrical characteristics would be superior. However, with the development of chip stacking technology (such as through silicon via technology), the electrical characteristics of system-in-package are comparable to those of system-on-chip. Figure 4 compares the signal transmission paths of system-on-chip and system-in-package using TSV stacking. When a signal is transmitted from one end of the SoC to the opposite end of the diagonal, the transmission path will be much shorter when the SoC is divided into 9 parts and stacked using through silicon via technology.
Figure 5: Concept diagram of core particles
In addition to system-in-package using through-silicon via stacks that have become the focus due to their various advantages, a technology called Chiplets has also received widespread attention in recent years. As shown in Figure 5, this technology splits existing logic chips according to functions and connects them through silicon via technology. Compared with single chips, core chips have three major advantages.
First of all, the yield of core chips is improved compared with that of single chips. When the size of the chip on the wafer (Wafer) is large, the wafer yield will be limited. Reducing the chip size can improve the wafer yield, thereby reducing manufacturing costs. For example, a 300 mm diameter wafer is cut into 100 or 1000 chips (die). If during wafer processing, five chips are defective due to five impurities evenly distributed on the front side of the wafer, the yield of the product cut into 100 chips will be 95%, while the yield of the product cut into 1,000 chips will be 95%. Then it is 99.5%. Therefore, products containing more die or smaller chip sizes have higher yields. For this reason, splitting the chip by function and treating it as a system-in-package rather than as individual chips in a system-on-a-chip can help improve cost-effectiveness.
The second advantage is that the development process is simplified. For a single chip, if you need to upgrade the chip function or adopt the latest technology, the entire chip needs to be redeveloped. However, if the chips are divided, only the chips with relevant functions need to be upgraded or developed using the latest technology, thus shortening the development cycle and improving process efficiency. For example, existing 20-nanometer (nm) technology can be used for some segmented chips, while the latest sub-10-nanometer technology can be used for other chips to improve development efficiency.
The third advantage is that it can promote the centralization of technology development. Because the chips are divided by function, there is no need to develop a corresponding chip for each function. Only the chips used for core technologies are developed, while other chips can be purchased or outsourced, so that companies can focus on developing their own core technologies.
In view of these advantages, major semiconductor manufacturers are introducing semiconductor products based on die technology or incorporating it into their development roadmaps.
In the previous article, we introduced various traditional and wafer-level packaging technologies, while this article provides an overview of more packaging technologies and their different characteristics. At present, stacked packaging and system-in-package technology have made great progress, and semiconductor researchers will continue to work on improving the capabilities of these high-quality technologies to improve their functionality while minimizing the space they occupy. The efficiency of the packaging process is expected to be further improved by producing packaged products that combine size, functionality and performance advantages.
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