Sharing of SPI and I2C communication solutions for nationally produced T3+FPGA
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Sharing of SPI and I2C communication solutions for nationally produced T3+FPGA

Posted Date: 2024-02-07

In recent years, with the continuous advancement of China's new infrastructure and Made in China 2025 plan, it has become increasingly difficult for a single ARM processor to meet the functional requirements of industrial sites. Especially nowadays, energy and power, industrial control, smart medical and other industries often require ARM more. + FPGA architecture processor platform to implement specific functions such as multi-channel/high-speed AD acquisition, multi-channel network ports, multi-channel serial ports, multi-channel/high-speed parallel DI/DO, high-speed data parallel processing, etc. Therefore, ARM + FPGA architecture processor The platform is becoming more and more popular in the market.


Therefore, Chuanglong Technology officially launched a 100% localized ARM + FPGA industrial core board a year ago, which is based on the Allwinner T3 + Unisoc Tongchuang Logos processor design.

Allwinner T3 is a quasi-car grade chip with a quad-core ARM Cortex-A7 architecture and a main frequency of up to 1.2GHz. It supports dual network ports, eight-channel UART, and SATA large-capacity storage interfaces. It also supports 4-channel display, GPU and 1080P H. 264 video hardware codec. In addition, Chuanglong Technology has adapted the domestic embedded system Yihui SylixOS on the T3 platform, truly realizing the localization of software and hardware.


Unisoc Logos PGL25G/PGL50G FPGA are widely used in the industrial field. The logic resources are 27072/51360 respectively. They are pin to pin compatible with foreign products from foreign companies and are mainly used for multi-channel/high-speed AD acquisition or interface expansion. Because of its low price, stable quality, and easy-to-use development environment, it has been widely praised by industrial users. Especially for the development environment, switching from foreign products to Unisoc’s products can be completed in as little as 3 days.

Figure 1 Typical application scenario of ARM + FPGA

SPI communication advantages and application scenarios

SPI (Serial Peripheral Interface) is a communication protocol for serial data transmission. SPI communication has the advantages of high bandwidth, strong real-time performance, fast transmission speed, simple connection, high reliability and flexibility.


The SPI protocol is suitable for communication needs between many embedded systems and peripheral devices, providing fast, reliable and flexible data transmission, which is very suitable for "Small data-low latency"and"Big Data - High Bandwidth” application scenarios.

Figure 2SPI communication bus

I2C communication advantages and application scenarios

I2C (Inter-Integrated Circuit) is a serial two-way communication protocol. I2C communication has the advantages of low hardware resource requirements, simplicity and flexibility, high reliability and support for multiple device types.


The I2C protocol provides simple, reliable and flexible data transmission. It is widely used in various fields such as sensors, storage devices, display devices and communication modules. Suitable for application scenarios that control naming transmission and system configuration.

Figure 3I2C communication bus


Introduction to SPI and I2C communication solutions of domestic T3+FPGA

This chapter mainly introduces the ARM + FPGA communication solution based on SPI and I2C between Quanzhi Technology T3 and Ziguang Tongchuang Logos. The hardware platform used is: Chuanglong Technology TLT3F-EVM industrial evaluation board.

I2C communication case

Case function:

Realize the TWI (I2C) communication function between T3 (ARM Cortex-A7) and FPGA.

The FPGA case source code is "4-Software Information Demofpga-demoi2c_slave", which implements the I2C Slave function and has built-in user-readable and writable registers, LED registers, and KEY registers.

As the I2C Master, the ARM side can read and write the FPGA side user-readable register 0x00 and the LED write register 0x01 through the TWI (I2C) bus (write 1 to light up the FPGA side LED, write 0 to turn it off), and check the KEY register 0x02 detection The user on the FPGA side inputs the button status.

Case test:Before powering on the evaluation board, please load and run the FPGA-side executable program first. Execute the following command to view the mounted devices on the I2C bus, where 0x2a is the address of the FPGA-side I2C Slave.


Target#echo "1 4 1 7" > /proc/sys/kernel/printk //Shield kernel printk printing to avoid printing warning messages when the I2C driver scans and cannot find the device.

Target#i2cdetect -r -y 0


Figure 4

Execute the following command to read and write the FPGA-side user-readable and writable register 0x00.


Target#i2cset -f -y 0 0x2a 0x00 0x55 //Write 0x55 to register 0x00

Target#i2cget -f -y 0 0x2a 0x00 //Read register 0x00, the value is 0x55

Figure 5


Execute the following command to write the FPGA-side LED register 0x01 to realize user-programmable indicator light control on the FPGA side.


Target#i2cset -f -y 0 0x2a 0x01 0xc0 //Write 0xc0 to LED register 0x01 to light up LED3 and LED4 on the FPGA side

Target#i2cset -f -y 0 0x2a 0x01 0x00 //Write 0x00 to LED register 0x01 to turn off LED3 and LED4 on the FPGA side

Figure 6


Execute the following command to read the KEY register 0x02 on the FPGA side to detect the status of the user input keys on the FPGA side.


Target#i2cget -f -y 0 0x2a 0x02 //Read KEY register 0x02, the value is 0xe0

Figure 7


Please press the user input button KEY7 on the FPGA side and keep it pressed, and then execute the following command.


Target#i2cget -f -y 0 0x2a 0x02 //Read KEY register 0x02, the value is 0xc0

Figure 8


Please press the user input button KEY8 on the FPGA side and keep it pressed, and then execute the following command.


Target#i2cget -f -y 0 0x2a 0x02 //Read KEY register 0x02, the value is 0xa0

Figure 9

Please press the user input button KEY9 on the FPGA side and keep it pressed, and then execute the following command.


Target#i2cget -f -y 0 0x2a 0x02 //Read KEY register 0x02, the value is 0x60

Figure 10

SPI communication case based on Linux

Case function:Based on the Linux system, the SPI communication function between T3 (ARM Cortex-A7) and FPGA is implemented.


The source code of the ARM side case is "4-Software Information Demomodule-demosspi_rw", which implements the SPI Master function, as follows:

(1) Open the SPI device node, such as: /dev/spidev0.1.

(2) Use ioctl to configure the SPI bus, such as SPI bus polarity and phase, communication rate, data length, etc.

(3) Select the mode as single-line mode or dual-line mode. When the SPI bus is set to dual-wire mode, sending data is in single-wire mode, and receiving data is in dual-wire mode.

(4) Send data to the SPI bus and read data from the SPI bus.

Verify the data, and then print the read and write rate and bit error rate.


The source code of the FPGA side case is "4-Software Information Demofpga-demosdram_spi" and "4-Software Information Demofpga-demosdram_spi_dual" to implement the SPI Slave function. The specific instructions are as follows: (1) Save the data sent by the SPI Master to DRAM. (2) When the SPI Master initiates reading data, the FPGA reads the data from the DRAM and transmits it to the SPI Master through the SPI bus. When the SPI bus is in dual-wire mode, receiving data supports dual-wire mode, while sending data only supports single-wire mode.

Figure 11

ARM side program flow chart

Case test:

When powering on the evaluation board, please load and run the FPGA-side executable program first. If you want to test in SPI single-wire mode, please run the program executable file in the "dram_spibin" directory of the case; if you want to test in SPI dual-wire mode, please run the "dram_spi_dualbin" directory. The program executable file under. At the same time, copy the ARM-side executable program spi_rw to any directory in the evaluation board file system.

Enter the evaluation board file system and execute the following command to view the newly generated spidev device node.


Target#ls /dev/spidev0.1

Figure 12


Execute the following command to query the program command parameters.


Target#./spi_rw -h


Figure 13


1SPI single wire mode


1.1 Functional testing


Execute the following command to run the program. ARM writes 1KByte random data to the FPGA DRAM through the SPI bus, then reads the data, performs data verification, and prints the SPI bus read and write rate and bit error rate. The final measured write rate is 2.405MB/s. , the reading rate is 2.405MB/s, and the bit error rate is 0. As shown below.


Target#./spi_rw -d /dev/spidev0.1-s 50000000 -OH -m 1 -S 1024-c 2


Parameter analysis:

-d: device node;

-s: Set the communication clock frequency (Hz). For this test, the SPI bus communication clock frequency is set to 50MHz. The theoretical communication rate of SPI single-line mode is: (50000000 / 1024 / 1024 / 8)MB/s ≈ 5.96MB/s;

-O: In idle state, SCLK is high level (CPOL=1);

-H: Start sampling from the second transition edge (CPHA=1);

-m: Select mode transmission mode (1 indicates single-line mode, 2 indicates dual-line mode);

-S: Set the transmission data size in Byte;

-c: The number of times to cyclically transmit data packets.

Figure 14


1.2 Performance test


(1) Based on 50MHz clock frequency


Execute the following command to run the program and test the maximum transmission rate of the SPI bus based on the 50MHz clock frequency and increasing the amount of read and write data. ARM writes 1MByte random data to the FPGA DRAM through the SPI bus, then reads the data without performing data verification, and finally prints the SPI bus read and write rate and bit error rate, as shown in the figure below.


Note: This case is designed to read and write 1KByte random data to FPGA DRAM at a time, so the bit error rate is high.


Target#./spi_rw -d /dev/spidev0.1-s 50000000 -OH -m 1 -S 1048576 -c 2

Figure 15


In this test, the SPI bus communication clock frequency is set to 50MHz, and the theoretical communication rate of SPI single-wire mode is: (50000000 / 1024 / 1024 / 8)MB/s ≈ 5.96MB/s. As can be seen from the above figure, the actual measured write rate this time is 5.757MB/s, and the read rate is 5.757MB/s, which is close to the theoretical communication rate.

This test SPI used DMA transmission, and the measured CPU occupancy rate was about 1%, as shown in the figure below.

Figure 16


(2) Based on 100MHz clock frequency


Execute the following command to run the program and test the maximum communication bandwidth of SPI single-wire mode based on 100MHz clock frequency. ARM writes 1MByte random data to FPGA DRAM through the SPI bus and reads the data out without performing data verification. Finally, it prints the SPI bus read and write rate and bit error rate, as shown in the figure below.


Note: This test is designed to test the maximum transmission rate of SPI. Currently, the SPI rate supports a maximum clock frequency of 50MHz. When the clock frequency is configured to a maximum of 100MHz, timing problems will occur in the rate. The phenomenon is that the overall speed is shifted to the right by 1 bit. For example, when sending 10000000, 01000000 is actually received, and a bit error occurs during the test.


Target#./spi_rw -d /dev/spidev0.1-s 100000000 -OH -m 1 -S 1048576 -c 100

Figure 17

According to the official data sheet (as shown below), the theoretical maximum SPI bus communication clock frequency is 100MHz. In this test, the SPI bus communication clock frequency is set to the maximum value of 100MHz, and the theoretical rate of SPI single-line mode is: (100000000 / 1024 / 1024 / 8)MB/s ≈ 11.92MB/s. As can be seen from the above figure, the measured SPI single-line mode write rate at 100MHz is: 11.331MB/s, and the SPI single-line mode read rate is: 11.331MB/s, which is close to the theoretical communication rate.

Figure 18


This test SPI used DMA transmission, and the measured CPU occupancy rate was about 1%, as shown in the figure below.

Figure 19

2SPI dual-wire mode


2.1 Functional testing


Execute the following command to run the program. ARM writes 1KByte random data to the FPGA DRAM through the SPI bus, then reads the data, performs data verification, and prints the SPI bus read and write rate and bit error rate, as shown in the figure below.


Target#./spi_rw -d /dev/spidev0.1-s 50000000 -OH -m 2 -S 1024-c 1


Parameter analysis:

-d: device node;

-s: Set the communication clock frequency (Hz). In this test, the SPI bus communication clock frequency is set to 50MHz, then the theoretical communication rate of SPI dual-wire mode is: (50000000 / 1024 / 1024 / 4)MB/s ≈ 11.92MB/s ;

-O: In idle state, SCLK is high level (CPOL=1);

-H: Start sampling from the second transition edge (CPHA=1);

-m: Select mode transmission mode (1 indicates single-line mode, 2 indicates dual-line mode);

-S: Set the transmission data size in Byte;

-c: The number of times to cyclically transmit data packets.

Figure 20


As can be seen from the figure above, the actual measured writing rate this time was 2.577MB/s, the reading rate was 5.222MB/s, and the bit error rate was 0.


2.2 Performance test


(1) Based on 50MHz clock frequency


Execute the following command to run the program and test the maximum transmission rate of the SPI bus based on the 50MHz clock frequency and increasing the amount of read and write data. ARM writes 1MByte random data to the FPGA DRAM through the SPI bus, then reads the data without performing data verification, and finally prints the SPI bus read and write rate and bit error rate. The final measured write rate this time is 5.892MB/s, and the read rate is 11.365MB/s. As shown below.


Note: This case is designed to read and write 1KByte random data to FPGA DRAM at a time, so the bit error rate is high.


Target#./spi_rw -d /dev/spidev0.1-s 50000000 -OH -m 2-S 1048576 -c 1

Figure 21


This test sets the SPI bus communication clock frequency to 50MHz, then the theoretical communication rate of SPI single-line mode is: (50000000/1024/1024/8)MB/s ≈ 5.96MB/s; the theoretical communication rate of SPI dual-line mode is: (50000000 / 1024 / 1024 / 4)MB/s ≈ 11.92MB/s.


This test SPI used DMA transmission, and the measured CPU occupancy rate was about 0%, as shown in the figure below.

Figure 22

(2) Based on 100MHz clock frequency


Execute the following command to run the program and test the maximum communication bandwidth of SPI dual-wire mode based on 100MHz clock frequency. The ARM writes 1MByte random data to the FPGA DRAM through the SPI bus and reads the data without data verification. Finally, the SPI bus read and write rate and bit error rate are printed. The final measured SPI dual-line mode write rate at 100MHz is: 11.684MB/ s, the SPI dual-wire mode read rate is: 23.432MB/s. As shown below.


Note: This test is designed to test the maximum transmission rate of SPI. Currently, the SPI rate supports a maximum clock frequency of 50MHz. When the clock frequency is configured to a maximum of 100MHz, timing problems will occur in the rate. The phenomenon is that the overall speed is shifted to the right by 1 bit. For example, when sending 10000000, 01000000 is actually received, and a bit error occurs during the test.


Target#./spi_rw -d /dev/spidev0.1-s 100000000 -OH -m 2-S 1048576 -c 100

Figure 23

According to the official data sheet (as shown below), the theoretical maximum SPI bus communication clock frequency is 100MHz. This test sets the SPI bus communication clock frequency to the maximum value of 100MHz, then the theoretical communication rate of SPI single-wire mode is: (100000000/1024/1024/8)MB/s ≈ 11.92MB/s; the theoretical communication rate of SPI dual-wire mode is: ( 100000000 / 1024 / 1024 / 4)MB/s ≈ 23.84MB/s.

Figure 24


This test SPI used DMA transmission, and the measured CPU occupancy rate was about 0%, as shown in the figure below.

Figure 25


SPI communication case based on Linux-RT


Case function: Based on Linux-RT real-time system, demonstrates the SPI communication function between T3 (ARM Cortex-A7) and FPGA. This case has a small amount of communication data, low bandwidth, but high real-time performance. It is suitable for industrial control occasions that do not require high communication bandwidth but have strict requirements for real-time communication.


The source code of the ARM side case is "4-Software Information Demomodule-demosrt_spi_rw", which implements the SPI Master function, as follows:

(1) Open the SPI device node. For example: /dev/spidev0.1.

(2) Use ioctl to configure the SPI bus. Such as SPI bus polarity and phase, communication rate, data word length, etc.

(3) Create a real-time thread.

(4) Send data to the SPI bus and read data from the SPI bus.

(5) Print sending and receiving rates and transmission time.

Verify the data, and then print the read and write rate and bit error rate.


The source code of the FPGA side case is "4-Software Information Demofpga-demosdram_spi", which implements the SPI Slave function, as follows: (1) Save the data sent by the SPI Master to DRAM. When the SPI Master initiates reading data, the FPGA reads the data from the DRAM and transmits it to the SPI Master through the SPI bus.

Figure 26

ARM side program flow chart

Case test:Since our company uses the latest Linux kernel by default, you need to refer to the "Replacing the Kernel and Kernel Module" chapter in the Linux system user manual document to replace the Linux system boot card with the Linux-RT system.


Before powering on the evaluation board, please load and run the FPGA-side executable program first. Copy the ARM-side executable file rt_spi_rw to any directory in the evaluation board file system, and execute the following command to view the newly generated spidev device node.


Target#ls /dev/spidev0.1

Figure 27


Execute the following command to query the program command parameters.


Target#./rt_spi_rw -h


Figure 28


1Non-polling method


Execute the following command to run the program. ARM writes random data to the FPGA DRAM through the SPI bus, then reads the data, performs data verification, and prints the SPI bus read and write rate, transmission time and bit error rate. The final measured minimum time is 44us, the maximum time consumption is 167us, the average time consumption is 48us; the write rate is 0.076MB/s, the read rate is 0.076MB/s, and the bit error rate is 0. As shown below.


Target#./rt_spi_rw -d /dev/spidev0.1 -s 50000000 -OH -S 4 -c 1024


Parameter analysis:

-d: device node;

-s: Set the communication clock frequency (Hz). This test sets the SPI bus communication clock frequency to 50MHz, and the theoretical communication rate is: (50000000 / 1024 / 1024 / 8)MB/s ≈ 5.96MB/s;

-O: In idle state, SCLK is high level (CPOL=1);

-H: Start sampling from the second transition edge (CPHA=1);

-S: Set the transmission data size in Byte;

-c: The number of times to cyclically transmit data packets.

Figure 29


2Polling method


Execute the following command to run the program. ARM writes 4Byte random data to the FPGA DRAM through the SPI bus, reads the data, performs data verification, and prints the SPI bus read and write rate, transmission time and bit error rate. The final measured minimum time is 27us, the maximum time consumption is 152us, the average time consumption is 30us; the write rate is 0.118MB/s, the read rate is 0.118MB/s, and the bit error rate is 0. As shown below.


Target#./rt_spi_rw -d /dev/spidev0.1-s 50000000 -OHp -S 4 -c 1024


Parameter analysis:

-d: device node;

-s: Set the communication clock frequency (Hz). This test sets the SPI bus communication clock frequency to 50MHz, and the theoretical communication rate is: (50000000 / 1024 / 1024 / 8)MB/s ≈ 5.96MB/s;

-O: In idle state, SCLK is high level (CPOL=1);

-H: Start sampling from the second transition edge (CPHA=1);

-p: The SPI sending end adopts polling mode (the amount of data sent each time is ≤64Byte);

-S: Set the transmission data size in Byte;

-c: The number of times to cyclically transmit data packets.

Figure 30


Review Editor Huang Yu



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