The performance characteristics, functions and applications of the full-duplex universal asynchronous receiver-transmitter SCC2619

“SCC2619 is a high-integration, low-power full-duplex common asynchronous receiver-transmitter UART launched by Philips. The chip’s receiving and sending speeds could be outlined individually, and the receiver adopts a triple buffering technique, which tremendously reduces the variety of occasions the CPU handles interrupts within the interrupt drive system. SCC2691 supplies a handshake technique between the receiver and the sender. When the receiver’s buffer is full, it might robotically invalidate the distant sender’s sending.

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Creator: Yu Liping, Wang Yan

introduction

1 Overview

SCC2619 is a full-duplex common asynchronous receiver/transmitter UART with excessive integration and low vitality consumption launched by Philips. The chip’s receiving and sending speeds could be outlined individually, and the receiver adopts a triple buffering technique, which tremendously reduces the variety of occasions the CPU handles interrupts within the interrupt drive system. SCC2691 supplies a handshake technique between the receiver and the sender. When the receiver’s buffer is full, it might robotically invalidate the distant sender’s sending. As well as, SCC2691 additionally has the next options:

△ The programmable information format is 5~8 information bits; non-compulsory parity bit; programmable cease bit.

△ 16-bit programmable counter/timer.

△ The baud fee of the transceiver could be outlined within the following methods: 18 fastened baud charges from 50~115.2K; non-standard customized baud fee pushed by counter/timer; 1 occasions the exterior clock or 16 occasions the frequency.

△ Parity examine, body error, overflow error detection.

△ Programmable channel mode.

△ 7 interrupt sources, however just one interrupt output on the identical time.

2 Pin definition

SCC2691 is packaged in SO, PLCC, DIP, and so on. The primary pin features are outlined as follows:

D0~D7: Knowledge bus. All information, instructions, standing info, and so on. between the CPU and the UART are transmitted by means of the information bus. When the CEN sign is energetic low, the sending course is set by the 2 read-write controls of WRN and RDN; when CEN is excessive, the information bus is tri-stated.

CEN: Chip allow pin, energetic low. When low degree is enabled, the information transmitted between CPU and UART by means of D0~D7 is managed by pins equivalent to WRN, RDN and A0~A2; when excessive degree, UART is remoted from CPU.

WRN: Write strobe, energetic low. When CEN is low, the low degree on WRN causes the information on the information bus D0~D7 to be despatched to the register chosen by the handle A0~A2.

RDN: Learn strobe, energetic low. When CEN is low degree, the low degree on RDN will ship the contents of the register chosen by the handle A0~A2 to the information bus D0~D7.

A0～A2: Deal with enter terminal. Choose the UART register to carry out learn and write operations.

RESET: Reset enter terminal, energetic at excessive degree. When reset, the standing register (SR), interrupt masks register (IMR), interrupt standing register (ISR) within the UART will probably be cleared, and the setting mode pointer factors to mode register 1 (MR1), which makes sending and receiving invalid, and the pin TxD is ready to Excessive degree.

INTRN: Interrupt request output terminal, energetic low. Certainly one of seven interrupt sources could be chosen because the interrupt output of UART. The CPU can learn the interrupt standing register (ISR) to find out the standing of the seven interrupt sources. This pin is an open-drain output and must be linked to a pull-up Resistor.

X1/CLK: Crystal connection or exterior clock enter terminal. Normally a 3.6864MHz crystal is used.

X2: Crystal connection terminal. If the crystal just isn't linked, it's best to depart this pin floating.

RxD: Serial information enter terminal.

TxD: Serial information output terminal. When the transmitter is idle, disabled, or the UART is working within the native loop state, this pin outputs a excessive degree.

MPO: Multi-function output terminal. By programming the auxiliary management register (ACR), the next 8 features could be chosen because the output of this pin.

① RTSN: Request to ship, low-level efficient. The pin could be enabled by programming the command register (CR), or the mode register (MR) could be set to robotically reset when the sender finishes sending or the receiver’s obtain buffer is full.

② C/TO: rely/timer output.

③ TxC1X: 1 occasions the frequency output of the transmitter frequency.

④ TxC16X: 16 occasions the frequency output of the transmitter frequency.

⑤ RxC1X: 1 occasions the frequency output of the receiver frequency.

⑥ RxC16X: 16 occasions the frequency output of the receiver frequency.

⑦ TxRDY: Signifies that the transmitter save register (THR) is empty. Lively low (open-drain output).

⑧ RxRDY/FFULL: Identifies that the receiver buffer just isn't empty or full. Lively low (open-drain output).

MPI: Multi-function enter pin. This pin could be outlined as the next 3 features:

① GPI: Basic function pin. The transition or degree standing on this pin can be utilized as an interrupt supply and mirrored to the corresponding little bit of the interrupt standing register (ISR).

② CTCLK: exterior enter clock of counter/timer.

③ RTCLK: The exterior clock enter of the receiver or transmitter. Set the clock choice register (CSR) to pick out the enter 1 occasions or 16 occasions because the frequency of receiving and sending.

3 principal features

(1) Interrupt management

The next inner occasions can allow the interrupt output pin (INTRN): the sending holding register (THR) is prepared; the sending switch register (TSR) is empty; the receiving holding register (RHR) is prepared or full; the break sign is acquired Begin or finish; the counter reaches the outlined rely worth; the transition of the MPI terminal pin; the extent state of the MPI terminal pin.

The registers associated to interrupt management are the interrupt masks register (IMR) and the interrupt standing register (ISR). IMR is used to pick out one of many above seven interrupt sources because the situation for triggering INTRN. The CPU can learn the ISR to get the standing of all interrupt sources. ISR just isn't affected by IMR.

(2) Operational management

The management logic unit of the UART receives instructions from the CPU and generates corresponding alerts to manage the operation of inner units. The management logic unit makes the CPU and UART talk with one another by means of handle decoding and read-write management. See Desk 1 for the connection between handle decoding and read-write management.

Desk 1 Register handle desk

Mode register 1 (MR1) and mode register 2 (MR2) are accessed by means of an auxiliary pointer. When the power-on reset or the reset command is executed by means of the command register (CR), the pointer factors to MR1, and any subsequent learn and write operations to MR1 will make the pointer level to MR2 and level to MR2 till the reset command is executed once more.

(3) Counter/timer

The working mode of the counter/timer and the choice of the enter clock supply could be chosen from eight modes by programming the auxiliary management register (ACR). The output of the counter/timer could be set because the multi-function output port MPO, and the output of the timer will also be used as one of many choices for producing the baud fee.

① Timing mode: The output of the timer is a sq. wave, the interval of which is twice the worth within the registers CTUR and CTLR. When the timer overflows, the counter prepared within the interrupt standing register (ISR) is ready. When an interrupt counter command is issued, the timer won't be terminated, solely the counter prepared bit within the ISR will probably be affected. When receiving a begin counting/timer command, the timer will terminate the present operation and begin a timing cycle with new CTUR and CTLR.

② Counting mode: After the counter receives the beginning counting command, it sends the rely worth to CTU and CTL. When the rely worth reaches the predetermined worth saved in CTUR and CTLR, the counter prepared place within the ISR is 1, and the counting operation won't cease till the top rely command is acquired. The CPU can set the registers CTUR and CTLR at any time, however this worth is barely legitimate when the present rely is ended and the subsequent rely command is began.

(4) Receiving and sending

The transmitter receives the parallel information from the CPU, converts it right into a serial information stream and sends it to the TxD port. The serial information stream is split right into a begin bit, a programmable variety of information bits, non-compulsory parity bits and programmable The mixed type of the variety of cease bits is shipped out. After the transmission is over, if no new information is shipped to the transmission holding register (THR), the TxD pin stays excessive, and the bit TxEMT within the standing register (SR) is ready to 1. When the CPU sends a brand new information to the THR, the TxEMT bit is cleared, and the sending operation continues. Concern a begin break command to make the transmitter ship a break sign (steady low degree). When the transmitter receives a command to terminate the transmission, whether it is sending information or there's nonetheless information within the THR, the transmitter will proceed to ship till the THR is empty.

The receiver receives serial information from the RxD pin, detects its begin bit, parity bit, and cease bit. If there's an error, it units the corresponding bit within the standing register (SR). The receiver sends the information to the obtain holding register (RHR), waits for the CPU to learn the information in question mode or interrupt mode, and units the RxRDY within the SR and the RxRDY little bit of the interrupt standing register (ISR) to 1.

The Obtain Holding Register (RHR) is a first-in first-out queue (FIFO) that may maintain 3 characters. The receiver sends the information acquired from RxD to the start of the FIFO and units RxRDY in SR to 1. RxRDY=1, it means there are acquired characters within the FIFO; and FFULL=1, it means the FIFO is full. Within the mode register 1 (MR1), you may choose RxRDY or FFULL because the obtain interrupt supply. Studying the RHR can pop the information in it from the FIFO together with the corresponding standing bit within the SR.

4 registers

The register is a bridge for operation between the CPU and the UART. The CPU controls the UART operation by means of programming registers. As well as, the modifications in varied standing registers additionally mirror the execution outcomes of the instructions.

5 Utility

(1) {Hardware} circuit

Determine 1 is an expanded serial port circuit designed utilizing SCC2691. Amongst them, AD0~AD7 are linked to the CPU (Yiheng C164CI) information bus; A12~A14 are linked to the CPU handle line; respectively are linked to the CPU’s learn and write alerts; RESET is linked to the CPU’s RESETOUT; 2691_CS is the chip choice sign of SCC2691; INTRN is linked to the CPU The interrupt enter terminal.

(2) Take a look at process

The take a look at program is developed within the Tasking C built-in atmosphere, and the particular program is within the community supplementary model.