The working principle of APB protocol bus in SOC design
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The working principle of APB protocol bus in SOC design

Posted Date: 2024-01-18

Now let’s talk about the nerve endings of the SOC. They are attached to the skeleton, controlled and regulated, and share external information to the core and other members. What is it?

It is what we call a standard bus. All modules on the SOC that want to be controlled by the core need to be mounted on the crossbar for configuration under the CPU and data transmission between the CPU and DMA. Let's start with the simplest APB bus to further understand the working principle of the standard bus.

1. Introduction to APB protocol

APB (Advanced Peripheral Bus), as an advanced peripheral bus, is one of the AMBA protocols and the most basic bus protocol. According to ARM's official definition, APB is a low-cost interface protocol that can achieve low power consumption and streamlined interface design, reducing the complexity of interface design.

The APB protocol does not support pipeline design. It is mainly used in interfaces with low bandwidth design requirements. The AXI bus can be used for high-performance bandwidth requirements. The implementation of the APB protocol is clock edge aligned to simplify the design of peripheral interfaces. Each transfer requires at least two clock cycles.

In SOC design, AHB is generally used as an IP configuration interface, including low-speed IP such as I2C, UART, I2S, etc., as well as high-speed IP such as DDR, PCIe, Ethernet, etc., which can easily realize the register configuration of the CPU's peripheral IP. The system generally implements an AXI2APB or AHB2APB conversion bridge to mount the APB port on the system.

The transmission signal of APB is only related to the rising edge of the clock, so it has the following advantages:

·Easy to implement high-frequency operation;

·Performance has nothing to do with clock duty cycle;

·Static timing analysis is simple;

·Easy to register access based on rising edge;

·Easy to integrate into cycle-based simulators.

1.1. Development history of APB

The protocol has evolved from APB2.0 to the current APB4.0. The specific differences are as follows:

·APB2.0: This version of the protocol defines basic interface signals (see the port signal chapter for details, just delete some interfaces in APB3.0);

·APB3.0: Added signal PREADY to indicate slave is ready for data, added signal PSLAVERR to represent transmission error;

·APB4.0: Add signal PROT protection type, add signal PSTRB to support byte-level access;

What is the difference between 2.0 and 3.0?

The difference between APB2.0 and APB3.0: APB3.0 provides a low-power interface and reduces the complexity of the interface. And APB3 adds two more signals than APB2:

PREADY: to expand APB transmission, mainly to increase the delay;

Error signal PSLVERR: to indicate transmission failure.

What is the difference between 3.0 and 4.0?

·Added two signals, PROT and PRSTB.

·PPROT is a protection signal used to support non-security transactions and secure transactions on APB.

·PSTRB is a write strobe signal used for sparse data transfer on the write data bus. APB4 is used less frequently.

APB protocol is backward compatible.

At present, the most commonly used socs are APB2.0 and APB3.0. Below we mainly introduce these two versions.

2.APB 2.0

2.1. APB2.0 signal list

Here we need to distinguish the difference between Master and Slave. Master is the host and Slave is the slave. There can be n slaves under one switchboard. All data transmission is controlled by the master and the slave responds. APB 1TO multi-bridge is needed here. APB bif does not require arbitration. It only needs to decode the address. If the address is in the domain of a slave, its PSELn and other control signals are raised. n is the slave number.

APB2.0 signal

2.2. State machine

Through the changes of PSELx and PENABLE signals, the APB bus is in the following three states:

state machine

·IDLE: PSELx and PENABLE are both 0, indicating that there is no communication request between the master and the slave, so it is in this state.

·SETUP: When the master and a slave are ready to transmit data, they will enter this state. At this time, PSELx=1 and PENABLE=0. It means that the master selects a slave and tells the slave that I am going to exchange data with you. Please be ready! This state will remain for one clock cycle and then enter the ENABLE state. This status can be given directly to wdata.

·ENABLE: At this time, PENABLE is pulled high, and the master and a certain slave perform data transmission, which lasts for one clock cycle. This state starts waiting for rdata.

When writing the master yourself, just output the control signal according to this state.

2.3. Write operation

The following is the timing diagram of the write transfer:

write timing

·T1~T2: At this stage, there is no interactive data between the master and a certain slave, so it is in the IDLE state.

·T2: At this moment, the master is ready to write data to a certain slave, so it enters the SETUP state and at the same time pulls the PSEL signal of a certain slave high and the PWRITE signal high. This means that the master tells a certain slave: I am about to When transmitting data with you, I am writing the data into you. Please be ready! Change the PADDR and PWDATA signals at the same time in order to meet the timing of the next rising edge.

·T2~T3: Maintain for one clock cycle.

·T3: At this time, the PENABLE signal is pulled high and wdata is actually written to addr.

·T3~T4: Maintain for one clock cycle.

·T4: Data transmission ends and returns to the initial state again.

2.4. Read operation

Read timing

·T1~T2: At this stage, the master has no interaction with a certain slave, so it is in the IDLE state.

·T2: At this moment, the master is ready to read data from a certain slave, so it enters the SETUP state, and at the same time pulls the PSEL signal of a certain slave high and the PWRITE signal low. This means that the master tells a certain slave: I am about to When transmitting data with you, I want to read your data. Please be ready! At the same time, PADDR is changed to meet the timing of the next T4 sampling edge.

·T2~T3: Maintain for one clock cycle.

·T3: At this time, the PENABLE signal is pulled high, indicating that the master has officially read out the data in a slave. Note that the data is sampled on the rising edge of the clock at the end of the ENABLE cycle, which is the T4 moment.

·T3~T4: Maintain for one clock cycle.

·T4: Data transmission ends and returns to the initial state again.

3.APB 3.0

The APB 3.0 protocol is based on the APB 2.0 protocol and adds two new signals, PREADY and PSLVERR; the PREADY signal is a signal used by the slave device to indicate whether the slave is ready, and PSLVERR indicates whether the data received by the slave is incorrect.

signal table

APB3.0 signal

3.1. Write operation

Write operation, no wait

Write without wait sequence

This situation is no different from APB2.0. When PENABLE is pulled high, it will check whether PREADY is pulled high. If it is pulled high, it means that the slave is currently ready for data transmission, and the data will be written to the slave on the rising edge 3.

Write operation, waiting

Written with waiting sequence

If after PENABLE is pulled high, it is found that PREADY is not pulled high, it means that the slave is not ready for data transmission. At this time, all signals remain unchanged until PREADY is pulled high, and the data is written on the rising edge 5.

3.2. Read operation

Read operation, no wait

Read without waiting time

This situation is no different from APB2.0. It is similar to the write operation without waiting, so I won’t go into details.

Read operation, there is a wait

Reading has waiting time

When PENABLE is pulled high, it is found that the PREADY signal has not been pulled high, indicating that the slave is not ready yet. At this time, it will wait until the PREADY signal is pulled high, and sample data at the rising edge 6.

3.3. Error feedback

PSLVERR to indicate error conditions on APB transmission. Errors can occur in both read and write transactions. When PSEL, PENABLE and PREADY are all high, PSLVERR is considered valid only during the last cycle of APB transmission, and PSLVERR is not considered at other times.

write operation

slverr write timing

On the basis of the previous waiting write operation, add PSLVERR, that is, sample at T4 time, and find that PSEL, PENABLE and PREADY are all high, and PSLVERR is high, indicating that there is an error in this data transmission. The software determines subsequent behavior.

Read operation

Read slverr timing

On the basis of the previous waiting read operation, add PSLVERR, that is, sample at T5 time, and find that PSEL, PENABLE and PREADY are all high, and PSLVERR is high, indicating that there is an error in this data transmission. The software determines subsequent behavior.

4. APB application scenarios.

APB is often used in peripherals because of its small area and few interfaces. Why?

Because there are many peripherals on the SOC, including spi, i2c, uart, timer, wdt, etc., they do not have high clock requirements. If you use the APB interface, you can save area and reduce the complexity of the chip. This is why the standard interface for peripheral priority is APB.

Here we mainly talk about some special uses of APB on SOC.

·Some IPs reserve user control signals. We need to use registers to control this signal. Generally, each subsystem of the SOC will have a module dedicated to doing this. In this case, you can choose the APB interface to configure these registers.

·Some IPs, such as SRIO and serdes, reserve user configuration interfaces. Synosys is called the cr configuration port, which is used for configuration or debugging. At this time we can write an APB2CR bridge ourselves.

·Inter-core communication module. The interrupt output is generated by writing the register. At this time, the APB interface can be used. Because the number of interrupts occurs is small and there are no performance requirements, APB can be used. It is simple.

·APB to sram interface or APB to fifo. The external interface of some modules is SRAM, which requires us to use an adapter bridge. We choose to use an appropriate AMBA bus based on performance; when self-developed module data cache involves asynchronous processing, the APB to FIFO design may be used.

But it also has limitations. It has low bandwidth and does not support pipelines, so do not use APB if the module has these requirements.

Review Editor: Huang Fei


#working #principle #APB #protocol #bus #SOC #design