Three-level circuit principles and common circuit topology analysis
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# Three-level circuit principles and common circuit topology analysis

Posted Date: 2024-01-22

Author: Hou Henry

As the performance requirements for inverters such as power density, efficiency, and output waveform quality gradually increase, Neutral Point Clamped (NPC) three-level topology inverters have been widely used. Typical The three-level topology includes diode NPC (NPC1), Conergy NPC (NPC2), and active NPC (ANPC), as shown in the figure below.

1. The output waveform has less harmonic components: Compared with the two-level inverter, the three-level inverter adds a zero-level path, and the phase voltage can output three levels, namely +Vdc/2, 0, - Vdc/2, according to the figure below, you can see that the voltage waveform output by the three-level inverter is closer to a sine wave and has lower THD.

2. The loss is reduced, the switching frequency is increased, and the system cost is reduced: For example, the voltage of the switching device in the NPC1 topology can be reduced to half of the original value, and the switching loss of the device is greatly reduced. Therefore, the switching frequency can be increased to reduce the size and cost of the output filter. , if the power level remains unchanged, the current at the output end can be reduced by increasing the bus voltage, thereby reducing the cost of the output cable.

3. Improved device reliability: In systems with the same voltage level, the blocking voltage of the device in the three-level topology is reduced, and the reliability of the device is improved.

4. Improve electromagnetic interference EMI: Since the dv/dt of the device is greatly reduced during the switching process, the system electromagnetic interference is improved.

Of course, the three-level topology also has some disadvantages, such as increased device cost, increased complexity of control algorithms, uneven loss distribution, and midpoint potential fluctuations. However, due to the unique advantages of the three-level topology, it has been widely used in photovoltaics, energy storage, and UPS. , APF and many other occasions are widely used. The common three-level topology is introduced below.

NPC1

1.1. Current path

In the above figure, the blue-green line is the conduction current path, and the purple line is the corresponding zero-level commutation path. A power factor of +1 corresponds to the two modes ① and ②, and a power factor of -1 corresponds to the two modes ③ and ④. state;

1.2. Loss distribution

Taking the simulation of the F3L225R12W3H3 device (NPC1) in a 100kW PCS as an example, the simulation conditions are Vdc=1000V, Vac=380V, Fsw=16kHz, Fout=50Hz. Under inverter conditions, the loss of NPC1 is mainly concentrated in the T1/T4 tubes. , including conduction loss and switching loss; T2/T3 is in the normally open state, and the loss is mainly conduction loss; D5/D6 conducts during commutation, and its losses include conduction loss and reverse recovery loss.

Under rectification conditions, losses are mainly concentrated in D1/D4 tubes and T2/T3 tubes. D1/D4 has conduction loss and reverse recovery loss, T2/T3 produces conduction loss and switching loss during commutation, and D2 /D3 and D5/D6 only have conduction losses.

NPC2

In the NPC2 topology, a pair of common emitter or common collector IGBTs and anti-parallel diodes are used to replace the NPC1 diode clamping function, reducing two diode devices. Among them, T1/T4 tubes bear the full bus voltage, and T2/T3 tubes Withstands half bus voltage.

2.1. Current path

The working mode of NPC2 is similar to NPC1. Under inverter conditions, during the positive half cycle, T2 remains in the normally open state, and T1 and D3 commutate; during the negative half cycle, T3 remains in the normally open state, and T4 and D2 commutate. Under rectification conditions, during the positive half cycle, T2 remains in the normally open state and commutates from D1 to T3/D2; during the negative half cycle, T2 commutates from D4 to T2/D3.

2.2. Loss distribution

Taking the simulation of the F3L500R12W3H7 device (NPC2) in 100kW PCS as an example, the simulation conditions are Vdc=1000V, Vac=380V, Fsw=16kHz, Fout=50Hz. In the NPC2 topology, T1/T4 are high-voltage devices, and the switching loss is larger. However, due to the reduced number of switching devices on the current path and smaller conduction losses, the NPC2 topology is more efficient in systems with medium and low switching frequencies. The increase in the number of devices on the current path in the NPC1 topology will produce greater conduction losses, but each device only withstands half the bus voltage, and the switching losses are greatly reduced, so it has more advantages at high frequencies.

Take the working conditions of Irms=150A, Vdc=730V, PF=1, M=1 as an example to simulate. Modules with the same current level and different withstand voltages are used to form two-level, NPC1 and NPC2 topologies. The total losses generated by each topology are The curve that changes with the switching frequency is shown in the figure above. It can be seen that the total loss of the two-level topology is small only at low frequencies. The total loss of the NPC1 and NPC2 topology has a crossover point at 16kHz. Before the crossover point, the overall loss of the NPC2 topology is lower than NPC1 topology has better efficiency. The increase rate of the total loss of NPC1 topology after the cross point is lower than that of NPC2 topology. The efficiency of NPC1 topology is better at high frequency. It is worth noting that the frequency of cross point also varies with the application conditions and specific devices. Characteristics vary slightly.

ANPC

Replacing the clamping diode in NPC1 with IGBT and anti-parallel diode forms the ANPC topology, which expands two zero-level commutation paths. More balanced losses can be achieved through the selection and control of the zero-level commutation paths. Distribution and smaller commutation loop noise.

3.1. Current path

ANPC has multiple paths to choose from for zero-level commutation in each mode. According to the different modulation algorithms, it is divided into ANPC-1, ANPC-2, and ANPC-1-00. The state tables of the three modulation algorithms As follows.

It can be seen that in ANPC-1, a short commutation loop is used for commutation, T2 and T3 perform switching actions at the frequency of the fundamental component of the output voltage, and the rest perform switching actions at the switching frequency (marked in dark gray in the table).

In ANPC-2, a long commutation loop is used for commutation, T2 and T3 perform switching actions at the switching frequency, and the rest perform switching actions at the frequency of the fundamental component of the output voltage.

ANPC-1-00 adds a '0' state based on ANPC-1. At this time, 0+ and 0- act as intermediate switching states when converting P to 0 and N to 0. The ANPC-1-00 modulation algorithm passes Two parallel commutation paths reduce the conduction loss at zero level. The above different modulation algorithms will produce different loss distributions.

This article mainly discusses the advantages of three-level inverter topology, commutation paths and loss distribution of common three-level topologies. The follow-up will focus on three-level double-pulse testing, blocking state voltage equalization issues, modulation strategies, etc. The content will be discussed with everyone, so stay tuned.

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