TSMC’s 1nm progress exposed! It is expected to invest over NT$1 trillion, is it really necessary?
Electronics Enthusiast Network (Text/Wu Zipeng) According to the latest news from Taiwanese media, TSMC’s 1nm process will be located in Chiayi Science Park. TSMC has proposed to the relevant administrative authorities a land requirement of 100 hectares, of which 40 hectares will be used to establish an advanced packaging plant first, and the subsequent 60 hectares. It will be used as a site for 1nm to build a factory.
Regarding this rumor, TSMC stated that there are many considerations in choosing a location to set up a factory. TSMC uses Taiwan, China as its main base, and does not rule out any possibility. It also continues to cooperate with the Authority to evaluate suitable semiconductor factory land.
Industry insiders estimate that TSMC’s 1nm investment may exceed the level of NT$1 trillion.
1nm is extremely technically difficult and may have reached its limit
1nm is defined by many people as the limit of chip manufacturing technology. The main reason is that 1nm has indeed approached the physical limit of transistor manufacturing and will cause many technical problems.
Currently, the main process structure of advanced processes is FinFET (Fin Field Effect Transistor), also known as 3D transistor. FinFET uses Gate to surround Fin to increase the equivalent W value, which can more effectively control the channel area, thereby better controlling the current flow, reducing leakage current, and effectively suppressing the short channel effect, improving the performance of the device. and energy efficiency.
The FinFET structure consists of thin (vertical) fins of a silicon body on a substrate, with gates surrounding the channel providing good three-sided control of the channel. From 22nm chips to 5nm, FinFET is the preferred structure. However, after reaching the 3nm process, the static current leakage problem becomes more and more serious - in the 3nm process, FinFET's ability to control current drops sharply, and the leakage current is also increasing.
TSMC plans to start using the third-generation process structure - GAA-FET (surround gate field effect transistor) in the 2nm process. Samsung has already started to use this structure in the 3nm process. By surrounding the Channel on all sides, GAA-FET achieves stronger control over the Channel and further reduces the impact of the short channel effect.
Source: Samsung Semiconductor
According to Samsung Semiconductor, the GAA structure has two forms: wire and sheet. Nanowire GAA must stack multiple layers of Wire to widen the total channel width, which makes the process more complex. In order to solve this problem, Samsung Semiconductor did not choose a wire type (Wire), but adopted a wider sheet (Sheet) form of GAA, which is MBCFET.
Source: Samsung Semiconductor
According to Taiwanese media reports, TSMC has officially and successfully implemented the GAA technology 2nm process. In terms of process progress, 1nm will not be ushered in immediately after 2nm, but 1.4nm. The current name may be 14A, and then it will be 1nm. TSMC has previously revealed that the company has begun to form a 1.4nm team in 2022, so it is not surprising to start 1nm research and development now.
In 1nm mass production, it is expected that Samsung and TSMC may also use GAA-FET, but it may be a further evolved version of GAA-FET. It was mentioned at the IEDM conference that one of the evolutionary architectures is the Forksheet architecture. Intel believes that a stacked CFET field effect transistor architecture can be used, which is also an improvement of GAA-FET. It is a stacked GAA-FET that stacks n-type and p-type MOS components together.
However, even with structural improvements, 1nm still needs to face many challenges, such as the more prominent quantum tunneling phenomenon. This phenomenon points out that when the chip manufacturing process reaches 1nm, electrons will undergo quantum tunneling, which will cause the performance of the transistor to be limited. Quantum tunneling is actually uncontrolled leakage of electricity, causing uncontrollable heating.
In order to make leakage controllable, material innovation is as important as structural innovation. In order to realize the 1nm process, the industry has long begun to develop new materials to meet new challenges. At present, the industry has proven that the 1nm process can be achieved using non-silicon materials. In 2019, IMEC proposed that 2D materials can achieve process nodes below 1nm. The material used at that time was molybdenum disulfide (MoS2). An important property of molybdenum disulfide is that it can be grown in a stable form, just one atom thick, with atomic precision at that scale.
TSMC is also exploring 2D materials. TSMC, MIT, and Nanyang Technological University jointly published a paper describing how single-layer materials are affected by metal conductive gaps. The paper points out that smaller transistors can be realized by using metallic bismuth and some semiconductor single-layer transition metal dichalcogenides. These 2D materials include molybdenum disulfide (MoS2), tungsten disulfide (WS2) and tungsten diselenide (WSe2) ).
Many industry players believe that 1nm mass production faces many problems and may have reached the limit of the chip manufacturing process.
1nm chips are very expensive, and the lithography machine alone exceeds US$400 million.
In addition to technical and material challenges, wafer foundries also need to bear cost and customer risks if they want to mass-produce 1nm, because the 1nm process is indeed too expensive.
An analysis report pointed out that if you want to manufacture 1nm chips, existing photolithography machines cannot meet the demand. ASML, the world's leading lithography machine company, predicts that it will update its new generation of lithography machines in 2025, that is, after 2nm mass production. Based on High NA technology, it will increase the NA index from the current 0.33 to 0.55, further improving the lithography resolution. . This next-generation lithography machine will be mainly used for mass production of the 1.4nm process. The price is very expensive, reaching US$400 million, which is 2.8 times the price of the existing lithography machine.
However, this may not be the limit. ASML stated that this 0.55NA numerical aperture EUV lithography machine should be able to support the manufacturing of at least 1.4nm chips, but for 1nm chips, there is currently no clear solution. Then, we can also understand that if it is necessary to redesign the lithography machine for 1nm, the price may be higher. However, the current US$150 million lithography machine and process costs have become a bit overwhelming for TSMC. Looking back at TSMC's gross profit margin from the fourth quarter of 2022 to the second quarter of 2023, it dropped from 62.2% to 54.1%. In this way, only Apple can afford it. It is reported that the price of each wafer of TSMC's 3nm process is about US$20,000, and that of 5nm is US$16,000. Taiwanese media pointed out that Apple, as the only 3nm user, has strong bargaining power and has pushed the cost of 3nm to a very low level, which in turn has put pressure on TSMC's gross profit margin. On the other hand, Qualcomm could have used 3nm to further narrow the performance gap with Apple's A series, but because the price was too high, it ultimately chose Samsung's process.
This is the case with 3nm. It is hard to imagine that we will have to go through 2nm and 1.4nm before we can reach 1nm. How high the cost of 1nm will be by then.
Although 1nm may face the situation that no one can afford it, the industry is still eager to mass produce 1nm. Not to mention TSMC and Samsung, which have launched an arms race, Intel is also confident in mass production of 1nm. Like TSMC, or even earlier than TSMC, Intel also has its own 1 trillion transistor chip packaging route. In this route Below, it also includes the 1nm manufacturing process.
According to previous reports, Japanese chip manufacturer Rapidus and the University of Tokyo are teaming up with French semiconductor research institute Leti to jointly develop 1nm chips. In addition, IBM and IMEC are also working on mass production of 1nm.
Of course, some people question the rationality of 1nm’s existence. According to expected data, the performance of 1nm chips may be improved by 20% to 30% compared to existing 5nm chips, while power consumption may be reduced by 25% to 40%. Less than 50% energy efficiency improvement requires paying several times or even dozens of times the cost. It may be difficult for the end market to accept such a chip.
However, those who agree believe that 1nm may open a new model of chip manufacturing through material innovation, etc. We cannot use today’s perspective to define future technological innovation, just like we moved from the micron era to the nano era, and 40nm entered 28nm. , the high cost and complexity of 1nm technology may also lead to further concentration in the semiconductor industry, but at the same time newer high-performance computing applications will emerge to enable the 1nm process.
Moore's Law is an economic law. Although it has slowed down, it is far from dead. According to the plans of manufacturers such as TSMC, the 1.4nm process is expected to be mass-produced in 2026, and then 1nm will be officially mass-produced in 2028. However, judging from the current situation, postponement is a high probability event.
1nm has broken through the limits of silicon materials. Therefore, in addition to the need for more advanced photolithography machines and other equipment, material innovation is also a major focus. In this process, the industry may explore a new process iteration path that will bring advanced The level of technology continues to advance downwards. Standing at the current node, it is too early to say that 1nm is too expensive and is completely unnecessary.
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