Understand and minimize the impact of jitter on high-speed links
Author: Bill Schweber
Clock oscillators provide timing to modern circuits by pacing system components. As system speeds increase to hundreds of MHz or higher, these clocks must be faster and have extremely low jitter, typically less than 100 femtoseconds (fs), to maintain system performance. These clocks must also maintain low jitter specifications over time and be independent of temperature and voltage.
Some jitter is caused by signal path noise and distortion, which can be reduced to some extent using repetitive clocking and retiming techniques. However, jitter is also generated by the clock source, which is usually an oscillator. This is due to various physical phenomena, including thermal noise, process defects, power supply noise, other external noise entering the clock oscillator, material stress, and many other subtle factors. Regardless of the source of clock jitter, designers must do everything possible to minimize inherent clock jitter because this defect is irreversible.
This article will discuss the jitter issue from multiple perspectives. It then introduces the different clock oscillators available from Abracon LLC and explains how to minimize jitter by matching the performance of the clock oscillator to the application.
Clock jitter is the deviation of a clock's edges from their ideal position in time. This jitter affects the timing precision and accuracy of the data signal transmission when the clock signal is paced, resulting in degraded signal-to-noise ratio (SNR) at the receiver decoding/demodulation circuitry or other system ICs. This results in higher bit error rates (BER), more retransmissions, and lower effective data throughput.
Because of its importance, clock jitter has been extensively analyzed in systems that carry signals from a source to a receiver through cables, connectors, or circuit boards. Depending on the application, clock jitter can be characterized in a variety of ways, including cycle-to-cycle jitter, period jitter, and long-term jitter (Figure 1).
Figure 1: The term “jitter” encompasses many timing variations, including cycle-to-cycle jitter, cycle-to-cycle jitter, and long-term jitter. (Image source: VLSI Universe)
・Cycle-to-cycle jitter represents the variation in clock periods between two consecutive cycles, independent of changes in frequency over time.
・Period jitter is the deviation of any clock period from its average period. It is the difference between the ideal clock period and the actual clock period and can be specified as root mean square (RMS) period jitter or peak-to-peak period jitter.
・ Long-term jitter is when a clock edge deviates from its ideal position over an extended period of time. This is somewhat similar to drifting.
Jitter can disrupt the timing used by other sub-functions, components or systems to recover low BER data, or disrupt the timing used to pace components, such as memory elements or processors in a synchronized system. As can be seen from the eye diagram in Figure 2, the intersection point of the bits is enlarged at this time.
Figure 2: In an eye diagram, jitter is seen as the expansion of critical timing intersections in the data stream. (Image credit: Kevin K. Gifford/Univ. of Colorado)
For serial data links, circuitry on the receiving end must attempt to re-establish its own clock to optimize decoding of the data stream. To do this, the circuit must be synchronized and locked to the source clock, typically using a phase-locked loop (PLL). Jitter affects the system's ability to achieve this accurately, thereby impairing the system's ability to recover data at a lower BER.
Note that jitter can be measured in both the time domain and the frequency domain; both are valid observations of the same phenomenon. Phase noise is a frequency domain view of the noise spectrum surrounding an oscillator signal, while jitter is a time domain measurement of the oscillator cycle timing accuracy.
Jitter measurements can be expressed in a variety of ways. Usually time units are used, such as "10 picoseconds (ps) jitter". Root mean square (RMS) phase jitter is a time domain parameter measured from phase noise (frequency domain). Jitter is sometimes also called phase jitter, which can cause confusion, but it is still a time domain jitter parameter.
As the link operating frequency and its clock accelerate from tens of MHz to hundreds of MHz or higher, the allowed jitter of the clock source decreases to approximately 100 fs or less. These frequencies are suitable for optical modules, cloud computing, networking and Fast Ethernet, all of which are functions and applications that require carrier frequencies between 100 MHz and 212/215 MHz and data transfer rates up to 400 Gbps.
Using a quartz crystal oscillator is the most common method of creating a stable, consistent clock signal with precise frequency. An associated oscillator circuit provides support for the crystal. There are many families of such circuits, each with different trade-offs. Crystals have been used in radio communications in the mid-frequency (300 kHz to 3 MHz) and high-frequency (3 MHz to 30 MHz) radio frequency bands since the 1930s.
A widely used method for generating low-jitter clocks is one of many variations on a PLL-based architecture. For example, Abracon's AX5 and AX7 ClearClock™ families of devices feature 5 × 3.2 mm and 5 × 7 mm packages, advanced PLL technology, and exceptional low-jitter performance (Figure 3).
Figure 3: The Abracon AX5 and AX7 clock oscillators use one of many PLL-based designs, but with subtle modifications to minimize jitter. (Image source: Abracon)
In addition to operating frequency and oscillator design, jitter performance is also affected by the physical size of the quartz crystal at the oscillator's core. As crystal size decreases, achieving excellent RMS jitter performance becomes more challenging.
For a clocking solution in the 100 MHz to 200 MHz frequency band that is smaller than the PLL-based AX5 and AX7 devices, a new oscillator architecture is required. Such smaller size requirements are typically associated with the latest generations of optical transceivers and modules. There are four established methods for designing clock oscillators in the 100 MHz to 200 MHz range:
1. Use a quartz oscillator with an inverted MESA quartz blank as the resonant element.
2. Use a quartz oscillator with the third overtone quartz blank as the resonant element.
3. Use an oscillator circuit based on a third overtone/fundamental mode quartz chip below 50 MHz or a temperature-compensated crystal oscillator below 50 MHz, and matched with an integer or fractional mode PLL integrated circuit.
4. Use an oscillator loop based on microelectromechanical systems (MEMS) resonators below 50 MHz and matched with integer or fractional mode PLL ICs
Option 1 neither provides the best RMS jitter performance nor is it the most cost-effective solution. Option 3 becomes complex and has performance drawbacks, while the MEMS resonator approach of Option 4 fails to meet the primary performance specification of maximum 200 fs RMS jitter. In contrast, Scheme 2 uses the optimally designed third overtone quartz blank and takes into account the optimization of the electrode geometry and cutting angle. This combination delivers the best results in terms of cost, performance and size.
Using this approach, Abracon developed the “third overtone” ClearClock solution (Figure 4). This device uses a quieter architecture to achieve excellent ultra-low RMS jitter performance and extremely high energy efficiency in a tiny package as small as 2.5 × 2.0 × 1.0 mm.
Figure 4: Abracon's "third overtone" ClearClock solution uses a quieter architecture to improve overall performance and energy efficiency. (Image source: Abracon)
In this approach, careful design of the third overtone crystal blank and proper filtering and "capture" of the desired carrier signal ensures excellent RMS jitter performance at the desired carrier frequency.
This architecture does not use the typical PLL approach, so there is no upconversion. Therefore, there is no need for standard PLL fractional or integer multiplication, and the final output frequency corresponds to the resonant frequency of the third overtone quartz crystal. Since there are no fractional or integer multiplications, the design is simplified and enables minimal jitter in the smallest possible size.
Specifications and actual performance
A clock oscillator is more than just a crystal and its analog circuitry. The clock oscillator includes buffering features to ensure that neither the oscillator output load nor its short- and long-term variations affect the performance of the device. The clock oscillator also supports a variety of differential digital logic output levels for circuit compatibility. This compatibility eliminates the need for external logic level translation ICs. Such an IC adds cost, floor space, and jitter.
Because clock oscillators use different supply rail voltages in many different applications, they must provide various supply voltages such as +1.8 V, +2.5 V, or +3.3 V, as well as customizations typically between 2.25 V and 3.63 V. value. The clock oscillator must also offer a choice of different output formats, such as low-voltage positive/pseudo-emitter coupled logic (LVPECL) and low-voltage differential signaling (LVDS), among others.
By looking at the AK2A and AK3A series of crystal clock oscillators, we can see what can be achieved through a deep understanding and integration of materials, design, construction and testing. The two series are similar, with the main differences being their size and maximum frequency.
AK2A Series: This family of crystal oscillators has nominal frequencies from 100 MHz to 200 MHz, operating voltages of 2.5 V, 3.3 V, and 2.25 V to 3.63 V, and features LVPECL, LVDS, and HCSL differential output logic.
All devices in this family have similar performance, including low RMS jitter. For example, the AK2ADDF1-100.000T is a 100.00 MHz, 3.3 V device with LVDS output and RMS jitter of 160.2 fs (Figure 5). It has excellent frequency stability of better than ±15 ppm over temperature and is available in a six-lead surface mount device (SMD) package measuring 2.5 × 2.0 × 1.0 mm.
Figure 5: Jitter is 160 fs for the AK2ADDF1-100.000T, a 3.3 V, 100 MHz device with LVDS output. (Image source: Abracon)
However, as clock frequency increases, jitter must be reduced to maintain system-level performance. For the 156.25 MHz LVDS oscillator AK2ADDF1-156.2500T, the typical RMS jitter drops to 83 fs.
AK3A series: The AK3A series devices are slightly larger than the AK2A series devices, with specific dimensions of 3.2 × 2.5 × 1.0 mm (Figure 6). A version is available with a specified frequency of 212.5 MHz, slightly above the 200 MHz limit of the AK2A series.
Figure 6: The AK3A (right) crystal oscillator is slightly longer and wider than the AK2A series (left); includes versions up to 212.5 MHz, compared to 200 MHz for the AK2A. (Image source: Abracon)
The overall specifications of this AK3A device are similar to the corresponding AK2A series devices. For example, the AK3ADDF1-156.2500T3 is a 156.25 MHz LVDS oscillator with a typical RMS jitter of 81 fs, which is slightly better than the corresponding device in the AK2A series.
The jitter of these two families varies based on operating frequency, operating voltage, package size, and output selection.
Other practical considerations
It is not enough for a clock oscillator to meet specifications when shipped from the factory. Like all components, especially analog and passive components, these oscillators will drift over time due to aging and internal stresses in the materials they are composed of.
These realities are especially challenging for high-performance clock oscillators because there is no easy or convenient way to correct or compensate for this drift by adding software or clever circuitry. However, there are ways to mitigate the effects of drift. This includes long burn-ins by the end user to accelerate oscillator aging, or the use of temperature-stabilized oscillators in oven-controlled enclosures. The former is time-consuming and poses a challenge to the supply chain, while the latter is bulky, costly and consumes a lot of power.
Recognizing that aging is a critical parameter, Abracon's ClearClock family of products delivers tight, comprehensive frequency accuracy throughout the entire end product life (10 to 20 years). Abracon ensures frequency stability of better than ±50 ppm over this period. For this purpose, third overtone crystals are carefully selected, manufactured, and conditioned to achieve a stability of ±15 ppm from -20°C to +70°C and a stability of ±15 ppm from -40°C to +85°C. Stability to ±25 ppm over °C range.
Engineering design always involves trade-offs. Abracon's AK2A and AK3A series feature a new generation (second generation) oscillator ASIC that offers improved jitter noise performance compared to its predecessors (first generation AK2 and AX3 respectively), ensuring ultra-low RMS jitter performance.
The price of this improvement is a slight increase in power consumption. Maximum current consumption has increased from 50 mA in the first generation to 60 mA in the second generation, but the current consumption of the low-voltage devices is only about half that of the first generation. As a result, the second generation ClearClock oscillator provides ultra-low RMS jitter while maintaining low power consumption.
The timing oscillator is at the heart of the data link or clock function, and its accuracy, jitter, and stability are critical parameters in achieving the required system-level performance, including high SNR and low BER. Through innovative material choices and architecture, higher clock frequencies can be achieved to meet the stringent performance specifications required by the industry and its various standards. The Abracon AK2A and AK3A series are housed in SMD packages measuring just a few mm per side and offer less than 100 fs jitter from 100 MHz to 200 MHz.
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