Use an Agile RF Transceiver in an Adaptive SDR Communication System for Aerospace and Defense
Aerospace and defense (ADEF) system designers face unrelenting demand for lower power and more compact communications systems that are capable of an agile response to a dynamic signals environment. Moving beyond traditional radio architectures, software-defined radio (SDR) technology can help meet the fast-changing requirements for ADEF radios, but SDR implementation has presented multiple challenges for meeting both the functional requirements and the need for reduced size, weight, and power (SWaP).
This article describes a more effective SDR solution from Analog Devices that can simplify the design of low-power, compact, and agile communications systems without compromising performance.
Emerging challenges drive more demanding requirements
Designers face a demand for more effective communications in a growing number of industrial and mission-critical applications, including secure radio communications, adaptive radar, electronic warfare, and enhanced GPS navigation. These new challenges drive a need for enhanced wideband operation, higher dynamic range, greater frequency agility, and reconfigurability. However, these more demanding functional requirements can conflict with the need for lower SWaP as communications systems move to smaller battery-powered platforms, including unmanned aerial vehicles (UAS) and portable units.
Design solutions based on traditional discrete superheterodyne radio architectures offer high performance, wide dynamic range, and minimal spurious noise. For designers, the challenge of isolating the desired signal from the intermediate frequency (IF) at the heart of this approach typically results in complex designs with high SWaP and little to no reconfigurability (Figure 1).
In contrast, direct conversion (zero-IF) architectures reduce both the filtering requirements and the need for very high-bandwidth analog-to-digital converters (ADCs), resulting in a simpler design that can be implemented on a single chip (Figure 2).
Despite its apparent advantages, the direct conversion architecture presents its own implementation challenges that have limited its widespread adoption. In this architecture, the signal is converted to a radio frequency (RF) carrier at the local oscillator (LO) frequency, but direct current (DC) offset errors and LO leakage can result in errors being propagated through the signal chain. Furthermore, differences in signal paths, even within the same chip, can introduce a gain or phase mismatch of the in-phase (I) and quadrature (Q) signal, resulting in a quadrature error that can compromise signal isolation.
SDR technology offers the potential to overcome the limitations of traditional radio architectures, but few solutions can address the broader requirements associated with ADEF applications. Using the Analog Devices’ ADRV9002 RF transceiver, developers can easily meet the need for greater performance and functionality with the lower SWaP demanded in these applications.
Integrated functionality delivers optimized performance with reduced SWaP
Supporting a frequency range from 30 megahertz (MHz) to 6,000 MHz, the ADRV9002 is a highly-integrated transceiver that contains all the RF, mixed signal, and digital functionality required to support a broad array of application requirements. Capable of both time division duplex (TDD) and frequency division duplex (FDD) operation, the device features separate dual-channel direct conversion receiver and transmitter subsystems that include programmable digital filters, DC offset correction, and quadrature error correction (QEC).
Within its on-chip synthesizer subsystem, the ADRV9002 features two distinct phase-locked loop (PLL) paths: one for the high-frequency RF path and another for the digital clocks and converter sampling clocks. Finally, the device’s digital signal processing block includes an Arm® M4 embedded processor that handles self-calibration and control functions (Figure 3).
Able to operate in either zero-IF mode or low-IF mode for phase-noise-sensitive applications, the ADRV9002 features transmitter and receiver subsystems offering complete signal chains. Each transmitter subsystem provides a pair of digital-to-analog converters (DAC), filters, and mixers that recombine I and Q signals and modulates them onto the carrier frequency for transmission.
Each receiver subsystem integrates a resistive input network for gain control that feeds a current mode passive mixer. In turn, a transimpedance amplifier converts the mixer’s current output to a voltage level that is digitized by an ADC with a high dynamic range. During available transmitter slots in TDD operation or in FDD applications where only one receiver system is used, unused receiver inputs can be used to monitor transmitter channels for LO leakage and QEC, or unused receiver inputs can be used to monitor power amplifier (PA) output signal levels.
The latter capability comes into play in the ADRV9002’s integrated digital pre-distortion (DPD) feature, which uses its monitored PA signal levels to apply the appropriate pre-distortion required to linearize the output. This capability enables the ADRV9002 to drive the PA closer to saturation, optimizing its efficiency.
Tuning power and performance
The ADRV9002 device provides a fully integrated solution in a 196-ball chip scale package (CSP) ball grid array (BGA), as well as minimizing size and weight for SDR ADEF communications systems. To help developers further optimize power consumption, the ADRV9002 integrates multiple features designed specifically to help developers find a suitable balance between performance and power.
At the block level, developers can deploy power scaling on individual signal path blocks to trade reduced performance for lower power consumption. In addition, the blocks in TDD receive (RX) and transmit (TX) frames can be disabled to sacrifice RX/TX or TX/RX turnaround times for lower power consumption. To further aid the developers’ ability to optimize power versus performance, each ADRV9002 receiver subsystems include two pairs of ADCs. One pair comprises high-performance sigma-delta ADCs, while the second pair can substitute when power consumption is critical.
For applications characterized by periodic stretches of inactivity, the ADRV9002’s RX monitor mode can be employed. In this mode, the ADRV9002 alternates between a minimal power sleep state and a detect state at a programmed duty cycle. In the detect state, the device activates a receiver and attempts to acquire a signal over a bandwidth and RX LO frequency programmed by the developer. If the device measures signal power level above the programmed threshold, the device exits monitor mode, and the ADRV9002’s blocks are powered up to handle the desired signal.
Rapid prototyping and development
To help engineers move quickly into evaluation, prototyping, and development, Analog Devices provides extensive hardware and software support of ADRV9002-based systems.
For hardware support, Analog Devices offers a pair of ADRV9002-based cards:
- ADRV9002NP/W1/PCBZ for low band applications operating in the 30 MHz to 3 gigahertz (GHz) range
- ADRV9002NP/W2/PCBZ for high band applications in the 3 to 6 GHz range
Equipped with FMC connectors, these cards support the onboard ADRV9002 with power regulation and hardware interfaces, as well as clock and multichip synchronization (MCS) distribution. The cards connect through their FMC connector to an FPGA motherboard, such as AMD’s ZCU102 evaluation board for power and application control.
Analog Devices provides a complete schematic and bill of materials (BOM) for its ADRV9002NP radio cards in its support package. The schematic and BOM provide an effective starting point for custom hardware development for most applications. Some applications require an additional RF front-end to meet specific signal conditioning requirements. For these applications, developers only need a few additional components to complete their design (Figure 4).
In this example, developers can quickly implement a suitable RF front-end using the following power management components from Analog Devices:
- ADRF5160 RF switch
- HMC8411 low noise amplifier (LNA)
- ADMV8526 digitally tunable bandpass filter
- HMC1119 RF digital step attenuator (DSA)
- HMC8413 driver amplifier
- HMC8205B PA
Analog Devices provides comprehensive software development support through documentation and downloadable software packages. Developers using the development hardware mentioned above can proceed with prototyping and development based on Analog Devices’ product line software or open-source software packages.
This article limits the following discussion to product line software. For more information about the open-source development methodology, see Analog Devices’ ADRV9001/2 Prototyping Platform User Guide. Analog Devices stipulates that the term “ADRV9001” in the company’s support documentation is meant as a family designator encompassing the ADRV9002 and other members of the ADRV9001 family. Consequently, references to ADRV9001 in the text or figures below apply to the ADRV9002 device that is the focus of this article.
Available through Analog Devices’ product line software development kit (SDK) distribution, the company’s Windows-based Transceiver Evaluation Software (TES) tool provides an accessible starting point for quickly configuring and evaluating transceiver performance.
During evaluation and prototyping with Analog Devices’ ADRV9002-based cards and AMD’s ZCU102 evaluation board, the TES tool provides a graphical user interface (GUI) for configuring the hardware and observing captured data (Figure 5).
In turn, the TES tool autogenerates C# code that can be compiled to the Linux environment, MATLAB environment, or Python. The SDK provides a complete set of software libraries and application programming interfaces (APIs), including the ADRV9001 API package developed for the AMD ZCU102 platform.
The SDK flow also directly supports migration from evaluation and prototyping with the evaluation board to the developer’s custom target environment (Figure 6).
In this migration flow, the developer lets the TES autogenerate code as before. However, instead of using it directly, the developer deploys an edited version of the generated code to the target platform. In practice, the required edits are confined mainly to removing function calls that reference hardware components recognized by the TES tool but not needed in the target system. The SDK architecture includes a hardware abstraction layer (HAL) interface between the ADRV9001 library and the developers’ hardware, so developers need only provide custom code that implements the HAL interface code for their specific hardware. As a result, developers can quickly move from evaluation using the Analog Devices cards and AMD board to development for their custom target environment.
ADEF applications face growing challenges in an increasingly complex signal environment. Along with meeting the demand for higher performance across a wider range of frequencies, developers need to lower SWaP to support the migration of these applications to battery-powered systems. Using a highly integrated transceiver from Analog Devices, developers can implement SDR solutions to more effectively address these requirements.
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