Virtual process troubleshooting and research using SEMulator3D

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Virtual process troubleshooting and research using SEMulator3D

Posted Date: 2024-01-29

SEMulator3D process modeling identifies process and design issues early in development, reducing development delays, wafer fabrication costs and time to market

Author: Brett Lowe, Manager, Semiconductor Processing and Integration Department, Semiverse Solutions Division, Lam Group

Modern semiconductor processes are extremely complex and contain hundreds or thousands of independent process steps that interact with each other. When developing these process steps, unexpected obstacles often arise between upstream and downstream process modules, resulting in extended development cycles and increased costs. In this article we will discuss how to use SEMulator3D®The Design of Experiments (DOE) functionality in .

In the manufacturing of 3D NAND memory devices, a key process module involves forming metal gates and word lines in memory cells. The process first involves depositing hundreds of alternating stacks of silicon dioxide and silicon nitride onto a substrate. Second, the memory hole array is patterned and etched on the stacked layer with minimum pattern spacing. At this point, the appearance of each layer of silicon nitride (which will become the word lines) becomes like a slice of Swiss cheese. Sidewall profile control is difficult to achieve during these process steps because of the high aspect ratio in the etching process and the extremely deep depth required for the memory cell holes. Therefore, deviations such as bending and distortion may occur during the etching process. Memory cell hole diameter and hole spacing can vary by up to 25% from top to bottom of the stack.

After depositing the memory cell material in the memory cell hole, a series of narrow slot trenches are patterned and etched on the outer edge of the block. After this second etch exposes the sacrificial silicon nitride in the sidewalls of the slit trench, it is laterally etched from edge to center until it is completely removed. (1) Subsequently, a barrier compound lining and conductive metal are deposited to fill the space from the edge of the silicon nitride layer to the middle. This process creates metal gate memory cells and word lines. (2) The distance from the outer memory cell hole to the inner edge of the slit trench is called the "gauge" (Figure 1). This conduction path provides a low resistance conductive path along the outer edge of the word line. The word line is very long, usually equal to the entire length of the memory block. To maintain the required memory switching speed, a high degree of control over the word line resistance is required.

Figure 1: Top view of the virtual model experiment, with different experimental conditions set for each experiment (a, b and c). a) There are large memory cell holes, gaps, and no word line conduction paths in the model. Word line gaps are marked red. Due to the small spacing between the memory cell holes, the voids induce closure. b) There are large memory cell holes in the model, the word line conduction path is normal, and there are no gaps. c) There are normal-sized memory cell holes in the model, and the word line conduction paths are normal.

We use the SEMulator3D model to better study the factors affecting word line resistance in 3D NAND. The study showed that simply removing the conductive material from the memory cell holes resulted in 3D NAND wordline resistance that was much greater than expected. This suggests that the process of removing the sacrificial silicon nitride, or replacing it with a conductive metal, creates voids that increase word line resistance. The SEMulator3D virtual model shows that if the memory cell hole is too large, or the hole spacing is too narrow, the lateral deposition path leading to the inside of the word line will be blocked and voids will be formed in the conductive metal (Figure 2).

Figure 2: SEMulator3D virtual model showing a three-plane cross-section of the edge of a word line. The metal conductor fill does not continue from the closure at the edge of the slot trench to the center of the word line. Current is conducted only through the liner, from the center of the word line to the closure.

We used the SEMulator3D process model to conduct 200 virtual model experiments with different memory cell hole diameters, track gauges and gap positioning. The word line resistance was simulated using the SEMulator3D electrical analysis software package, and then the word line resistance was extracted from the virtual model experiment, and a comparison chart of the percentage increase in resistance versus track pitch, memory cell aperture increase, and voids was plotted (Figure 3) .

Figure 3 shows the effect of void formation on word line resistance. If you compare the word line resistance increase without gaps (red line) and the word line resistance increase with gaps (blue line), the effect of gaps is more obvious. Regardless of the size of the memory hole, the presence of the void increases the word line resistance by 55%. After increasing the outer track pitch, the impact of memory cell hole size on word line resistance is reduced by 200%, and the impact of introduced gaps on word line resistance is reduced to a negligible level. The results show that word line resistance increases with memory hole size.

Figure 3: Plot of increase in word line resistance (in percent) versus increase in memory cell hole diameter (in percent) and track gauge (in nm). The red line represents the result of the model including the wordline gaps (correct), and the blue line represents the result of the model removing the wordline gaps and filling them (wrong).

As the track pitch approaches zero, more current is forced into the inner region of the word line. As the storage pore size increases, the void size increases and the volume between the low-resistance conductive metal and the higher-resistance barrier compound lining decreases (Figure 4). When the word line track is preserved, the dependence of word line resistance on memory hole size and metal voids is minimized.

Figure 4: Top view of the current density in the virtual model experiment. Each setting (shown in Figures a, b and c) changes according to different experiments (see Figure 1). a) The conduction path is discontinuous, causing current to flow into the word line. b) The memory hole size is the same as in Figure a, but the wider conduction path allows current to flow along the outer edge of the word line. c) Wordline track pitch produces a more uniform current density pattern.

Using SEMulator3D void localization, the virtual model can predict the effect of voids on word line resistance without considering the memory hole size. In actual silicon wafer processes, there is no way to conduct separate experiments on void formation and memory cell hole size in 3D NAND process development. SEMulator3D enables experiments that are difficult or impossible to perform in the fab.

We used SEMulator3D process modeling to simulate the 3D NAND word line formation process. We observed that the upstream memory cell void module negatively affects the downstream word line forming module and results in a drastic increase in word line resistance. Using virtual models, we were able to simulate problems between upstream and downstream modules and explore potential solutions (in our case, the solutions involved design adjustments) using multiple experiments. SEMulator3D process modeling identifies process and design issues early in development without the need for extensive silicon wafer experimentation, which reduces development delays, wafer fabrication costs and time to market.


[1] Handy, “An Alternative Kind of Vertical 3D NAND String”, Jim Handy, Objective Analysis, on Semiconductor Memories, Nov 8, 2013.
[2] A. Goda, “Recent Progress on 3D NAND Flash Technologies”, Electronics2021, 10(24), 3156.

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