What is the Foveros package? Difficulties of Foveros packaging
This is Intel's 3D chip stacking technology.
Foveros packaging technology is a 3D packaging technology introduced by Intel that stacks computing modules vertically during the processor manufacturing process instead of the traditional horizontal way. This technology makes chip manufacturing more efficient while also helping to optimize cost and energy efficiency. Foveros packaging technology enables Intel and its foundry customers to integrate different computing chips and achieve more complex heterogeneous chip production in a single package. It is considered a very important technology that can lay the foundation for future innovations in advanced packaging technology.
Instead of one die moving on top of another die, which is essentially just a dense collection of wires, Foveros involves two dies that contain moving elements. With this, Intel's first generation Foveros was launched in June 2020 in the Lakefield hybrid CPU SOC. The chip isn't a particularly large or breathtaking chip, but it is Intel's first for many, including 3D packaging and their first hybrid CPU core architecture with large performance cores and small efficiency cores. It uses a bump pitch of 55 microns.
According to reports, most Intel client products, including the 13th generation Intel Core processors, integrate multiple functions (such as CPU, GPU, PCH) onto a single chip called SoC, but as these functions become increasingly diverse ation and becoming more and more complex, it is becoming more and more difficult and costly to design and manufacture these monolithic system-on-chips.
Intel's Foveros advanced packaging technology solves this challenge in one fell swoop. It uses high-density, high-bandwidth, and low-power interconnections to combine many modules manufactured using multiple process technologies into a chip complex composed of a large discrete module architecture.
As an innovative technology of Intel, Foveros packaging technology does face some technical difficulties.
First of all, the core of Foveros technology is to achieve 3D stacking of chips, which involves how to accurately align and connect different chips. Since the spacing between chips is very small, the accuracy of alignment is very high, which requires high-precision manufacturing equipment and process control technology.
Secondly, 3D stacking technology needs to solve the electrical connection problem between different chips. Since there may be differences in thickness, materials and processes between different chips, special design and optimization are required to ensure signal transmission quality and stability.
Foveros technology also needs to solve heat dissipation issues. Since the chips are 3D stacked, the heat dissipation path becomes more complex and difficult. How to effectively conduct heat away from stacked chips and distribute it to a heat sink or cooling system is a difficult problem that needs to be overcome.
The production cost of Foveros technology is also an issue to consider. Although this technology can improve the integration density and performance of chips, its manufacturing cost is also relatively high. Therefore, how to balance the relationship between technical performance and production costs is one of the challenges Intel needs to face.
As an innovative technology, Foveros packaging technology has technical difficulty and cost that need to be considered and solved. However, with the continuous advancement of technology and the increase in application requirements, it is believed that Foveros technology will be more widely used and developed.
Review Editor: Huang Fei
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